Changeset 406 for trunk/hal/tsar_mips32/core/hal_kentry.h
- Timestamp:
- Aug 29, 2017, 12:03:37 PM (7 years ago)
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- 1 edited
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trunk/hal/tsar_mips32/core/hal_kentry.h
r279 r406 24 24 #define _HAL_KENTRY_H_ 25 25 26 ////////////////////////////////////////////////////////////////////////////////////////// 27 // This file defines the MIPS32 specific mnemonics to access the "uzone", that is 28 // a fixed size array of 32 bits integers, used by the kentry function to save/restore 29 // the MIPS32 CPU registers, at each exception / interruption / syscall. 30 // It also defines several initial values for the SR register. 31 // 32 // This file is included in the hal_kentry.S, hal_syscall.c, hal_exception.c, 33 // and hal_context.c files. 34 ////////////////////////////////////////////////////////////////////////////////////////// 26 35 27 #define CPU_IN_KERNEL 1 36 37 /**************************************************************************************** 38 * This structure defines the cpu_uzone for TSAR MIPS32, as well as the 39 * mnemonics used by the hal_kentry assembly code. 40 ***************************************************************************************/ 41 42 #define UZ_MODE 0 /* c2_mode */ 43 #define UZ_AT 1 44 #define UZ_V0 2 45 #define UZ_V1 3 46 #define UZ_A0 4 47 #define UZ_A1 5 48 #define UZ_A2 6 49 #define UZ_A3 7 50 #define UZ_T0 8 51 #define UZ_T1 9 52 #define UZ_T2 10 53 #define UZ_T3 11 54 #define UZ_T4 12 55 #define UZ_T5 13 56 #define UZ_T6 14 57 #define UZ_T7 15 58 #define UZ_T8 16 59 #define UZ_T9 17 60 #define UZ_S0 18 61 #define UZ_S1 19 62 #define UZ_S2 20 63 #define UZ_S3 21 64 #define UZ_S4 22 65 #define UZ_S5 23 66 #define UZ_S6 24 67 #define UZ_S7 25 68 #define UZ_S8 26 69 #define UZ_GP 27 70 #define UZ_RA 28 71 #define UZ_EPC 29 /* c0_epc */ 72 #define UZ_CR 30 /* c0_cr */ 73 #define UZ_SP 31 74 #define UZ_SR 32 /* c0_sr */ 75 #define UZ_LO 33 76 #define UZ_HI 34 77 78 #define UZ_REGS 35 79 80 /************************************************************************************* 81 * The hal_kentry_enter() function is the unique kernel entry point in case of 82 * exception, interrupt, or syscall for the TSAR_MIPS32 architecture. 83 * 84 * When we enter the kernel, we test the status register: 85 * - If the core is in user mode, we desactivate the MMU, and we save 86 * the core context in the uzone of the calling thread descriptor. 87 * - If the core is already in kernel mode (in case of interrupt), 88 * we save the context in the kernel stack. 89 * - In both cases, we increment the cores_in_kernel variable, 90 * and we call the relevant exception/interrupt/syscall handler 91 * 92 * When we exit the kernel after handler execution: 93 * - we restore the core context from the uzone and return to user space, 94 * calling the hal_kentry_eret() 95 ************************************************************************************/ 96 void hal_kentry_enter(); 97 98 /************************************************************************************* 99 * The hal_kentry_eret() function contains only the assembly "eret" instruction, 100 * that and the EXL bit in the c0_sr register, and jump to the address 101 * contained in the c0_epc register. 102 * ************************************************************************************/ 103 void hal_kentry_eret(); 28 104 29 105 #endif /* _HAL_KENTRY_H_ */
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