Changeset 407 for trunk/hal/tsar_mips32

Timestamp:

Nov 7, 2017, 3:08:12 PM (7 years ago)

Author:

alain

Message:

First implementation of fork/exec.

Location:

trunk/hal/tsar_mips32

Files:

• core/hal_context.c (modified) (7 diffs)
• core/hal_drivers.c (modified) (7 diffs)
• core/hal_exception.c (modified) (10 diffs)
• core/hal_gpt.c (modified) (16 diffs)
• core/hal_interrupt.c (modified) (1 diff)
• core/hal_kentry.S (modified) (2 diffs)
• core/hal_kentry.h (modified) (1 diff)
• core/hal_ppm.c (modified) (2 diffs)
• core/hal_special.c (modified) (4 diffs)
• core/hal_switch.S (modified) (3 diffs)
• core/hal_syscall.c (copied) (copied from trunk/hal/tsar_mips32/core/hal_syscall.c) (3 diffs)
• core/hal_types.h (modified) (1 diff)
• core/hal_user.c (added)
• core/hal_uspace.c (modified) (4 diffs)
• drivers/soclib_bdv.c (modified) (2 diffs)
• drivers/soclib_dma.c (modified) (1 diff)
• drivers/soclib_hba.c (modified) (2 diffs)
• drivers/soclib_pic.c (modified) (12 diffs)
• drivers/soclib_pic.h (modified) (4 diffs)
• drivers/soclib_tty.c (modified) (11 diffs)
• drivers/soclib_tty.h (modified) (3 diffs)

trunk/hal/tsar_mips32/core/hal_context.c

@@ -44 +44 @@
 
 /////////////////////////////////////////////////////////////////////////////////////////
-// This structuree defines the cpu_context for TSAR MIPS32.
-// These registers are saved/restored at each context switch.
+// This structure defines the CPU context for TSAR MIPS32.
+// The following registers are saved/restored at each context switch:
+// - GPR : all, but (zero, k0, k1), plus (hi, lo)
+// - CP0 : c0_th , c0_sr , C0_epc
+// - CP2 : c2_ptpr , C2_mode
+//
 // WARNING : check the two CONFIG_CPU_CTX_SIZE & CONFIG_FPU_CTX_SIZE configuration 
 //           parameterss when modifying this structure.
@@ -85 +89 @@
     uint32_t gp_28;      // slot 28
         uint32_t sp_29;      // slot 29
-        uint32_t fp_30;      // slot 30
+        uint32_t s8_30;      // slot 30
         uint32_t ra_31;      // slot 31
 
@@ -108 +112 @@
 
 /////////////////////////////////////////////////////////////////////////////////////////
-//        CPU context access functions
-/////////////////////////////////////////////////////////////////////////////////////////
-
-/////////////////////////////////////////////////////////////////////////////////////////
-// This function allocates and initializes the cpu_context stucture in thread descriptor.
-// The following context slots are initialised by this function:
-// GPR : a0_04 / sp_29 / fp_30 / ra_31
+//        CPU context related functions
+/////////////////////////////////////////////////////////////////////////////////////////
+
+
+//////////////////////////////////////////////////
+error_t hal_cpu_context_alloc( thread_t * thread )
+{
+    assert( (sizeof(hal_cpu_context_t) <= CONFIG_CPU_CTX_SIZE) , __FUNCTION__ ,
+    "illegal CPU context size" );
+
+    // allocate memory for cpu_context
+    kmem_req_t  req;
+    req.type   = KMEM_CPU_CTX;
+    req.flags  = AF_KERNEL | AF_ZERO;
+
+    hal_cpu_context_t * context = (hal_cpu_context_t *)kmem_alloc( &req );
+    if( context == NULL ) return -1;
+
+    // link to thread
+    thread->cpu_context = (void *)context;
+    return 0;
+
+}   // end hal_cpu_context_alloc()
+
+///////////////////////////////////////////////////
+// The following context slots are initialised :
+// GPR : a0_04 / sp_29 / ra_31
 // CP0 : c0_sr / c0_th / c0_epc
 // CP2 : c2_ptpr / c2_mode
-/////////////////////////////////////////////////////////////////////////////////////////
+///////////////////////////////////////////////////
 error_t hal_cpu_context_create( thread_t * thread )
 {
-    kmem_req_t  req;
-
-    assert( (sizeof(hal_cpu_context_t) <= CONFIG_CPU_CTX_SIZE) , __FUNCTION__ ,
-    "inconsistent CPU context size" );
-
-    context_dmsg("\n[DMSG] %s : enters for thread %x in process %x\n",
-                 __FUNCTION__ , thread->trdid , thread->process->pid );
-
-    // allocate memory for cpu_context
-    req.type   = KMEM_CPU_CTX;
-    req.flags  = AF_KERNEL | AF_ZERO;
-
-    hal_cpu_context_t * context = (hal_cpu_context_t *)kmem_alloc( &req );
-    if( context == NULL ) return ENOMEM;
-
-    // set cpu context pointer in thread
-    thread->cpu_context = (void*)context;
-
-    // stack pointer, status register and mmu_mode depends on thread type
-        uint32_t sp_29;
-    uint32_t c0_sr;
-    uint32_t c2_mode;
+    // allocate memory for a CPU context
+    error_t error = hal_cpu_context_alloc( thread );
+
+    if( error ) return error;
+
+    hal_cpu_context_t * context = (hal_cpu_context_t *)thread->cpu_context;
+
+    // initialisation depends on thread type
     if( thread->type == THREAD_USER )
     {
-        sp_29   = ((uint32_t)thread->u_stack_base) + thread->u_stack_size;
-        c0_sr   = SR_USR_MODE;
-        c2_mode = 0xF;
+        context->a0_04   = (uint32_t)thread->entry_args;
+        context->sp_29   = (uint32_t)thread->u_stack_base + (uint32_t)thread->u_stack_size - 8;
+        context->ra_31   = (uint32_t)&hal_kentry_eret;
+        context->c0_epc  = (uint32_t)thread->entry_func;
+        context->c0_sr   = SR_USR_MODE;
+            context->c0_th   = (uint32_t)thread; 
+            context->c2_ptpr = (uint32_t)((thread->process->vmm.gpt.ppn) >> 1);
+        context->c2_mode = 0xF;
     }
-    else
+    else  // kernel thread
     {
-        sp_29   = ((uint32_t)thread->k_stack_base) + thread->k_stack_size;
-        c0_sr   = SR_SYS_MODE;
-        c2_mode = 0x3;
+        context->a0_04   = (uint32_t)thread->entry_args;
+        context->sp_29   = (uint32_t)thread->k_stack_base + (uint32_t)thread->k_stack_size - 8;
+        context->ra_31   = (uint32_t)thread->entry_func;
+        context->c0_sr   = SR_SYS_MODE;
+            context->c0_th   = (uint32_t)thread; 
+            context->c2_ptpr = (uint32_t)((thread->process->vmm.gpt.ppn) >> 1);
+        context->c2_mode = 0x3;
     }
 
-    // align stack pointer on a double word boundary 
-        sp_29 = (sp_29 - 8) & (~ 0x7);
-
-    // initialise context
-    context->a0_04      = (uint32_t)thread->entry_args;
-        context->sp_29      = sp_29; 
-        context->fp_30      = sp_29;                               // TODO check this [AG]
-    context->ra_31      = (uint32_t)&hal_kentry_eret;
-    context->c0_epc     = (uint32_t)thread->entry_func;
-        context->c0_sr      = c0_sr;
-        context->c0_th      = (uint32_t)thread; 
-        context->c2_ptpr    = (uint32_t)((thread->process->vmm.gpt.ppn) >> 1);
-        context->c2_mode    = c2_mode;
-
-    context_dmsg("\n[DMSG] %s : exit for thread %x in process %x\n"
+context_dmsg("\n[DBG] %s : thread %x in process %x\n"
                  " - a0   = %x\n"
                  " - sp   = %x\n"
-                 " - fp   = %x\n"
                  " - ra   = %x\n"
                  " - sr   = %x\n"
@@ -180 +184 @@
                  " - mode = %x\n",  
                  __FUNCTION__ , thread->trdid , thread->process->pid,
-                 context->a0_04, context->sp_29, context->fp_30, context->ra_31,
+                 context->a0_04, context->sp_29, context->ra_31,
                  context->c0_sr, context->c0_th, context->c0_epc,
                  context->c2_ptpr, context->c2_mode );
@@ -201 +205 @@
            ctx->c2_ptpr , ctx->c2_mode );
 
-}  // end hal_context_display()
-
-/////////////////////////////////////////////////////////////////////////////////////////
-// These registers are saved/restored to/from CPU context defined by <ctx> argument.
-// - GPR : all, but (zero, k0, k1), plus (hi, lo)
-// - CP0 : c0_th , c0_sr , C0_epc
-// - CP2 : c2_ptpr , C2_mode
-/////////////////////////////////////////////////////////////////////////////////////////
-// old_thread  : pointer on current thread descriptor
-// new_thread  : pointer on new thread descriptor
-/////////////////////////////////////////////////////////////////////////////////////////
-void hal_cpu_context_switch( thread_t * old_thread,
-                             thread_t * new_thread )
-{
-    hal_cpu_context_t * ctx_old = old_thread->cpu_context;
-    hal_cpu_context_t * ctx_new = new_thread->cpu_context;
-
-    #if CONFIG_CONTEXT_DEBUG
-    hal_cpu_context_display( old_thread );
-    hal_cpu_context_display( new_thread );
-    #endif
-
-    // reset loadable field in new thread descriptor 
-    new_thread->flags &= ~THREAD_FLAG_LOADABLE;
-
-    hal_do_switch( ctx_old , ctx_new );
-}
-
-/////////////////////////////////////////////
-error_t hal_cpu_context_copy( thread_t * dst,
-                              thread_t * src )
-{
-    kmem_req_t  req;
-
-    // allocate memory for dst cpu_context
-    req.type   = KMEM_CPU_CTX;
-    req.size   = sizeof(hal_cpu_context_t);
-    req.flags  = AF_KERNEL | AF_ZERO;
-
-    hal_cpu_context_t * dst_context = (hal_cpu_context_t *)kmem_alloc( &req );
-    if( dst_context == NULL ) return ENOMEM;
-
-    // set cpu context pointer in dst thread
-    dst->cpu_context = dst_context;
-
-    // get cpu context pointer from src thread
-    hal_cpu_context_t * src_context = src->cpu_context;
-
-    // copy CPU context from src to dst
-    memcpy( dst_context , src_context , sizeof(hal_cpu_context_t) );
-
-    return 0;
-
-}  // end hal_cpu_context_copy()
+}  // end hal_cpu_context_display()
 
 /////////////////////////////////////////////////
@@ -268 +219 @@
 
 
-///////////////////////////////////////////////////
-error_t hal_fpu_context_create( thread_t * thread )
-{
+
+
+
+//////////////////////////////////////////////////
+error_t hal_fpu_context_alloc( thread_t * thread )
+{
+    assert( (sizeof(hal_fpu_context_t) <= CONFIG_FPU_CTX_SIZE) , __FUNCTION__ ,
+    "illegal CPU context size" );
+
+    // allocate memory for fpu_context
     kmem_req_t  req;
-
-    assert( (sizeof(hal_fpu_context_t) <= CONFIG_FPU_CTX_SIZE) , __FUNCTION__ ,
-    "inconsistent FPU context size" );
-
-    // allocate memory for uzone
     req.type   = KMEM_FPU_CTX;
     req.flags  = AF_KERNEL | AF_ZERO;
 
     hal_fpu_context_t * context = (hal_fpu_context_t *)kmem_alloc( &req );
-    if( context == NULL ) return ENOMEM;
-
-    // set fpu context pointer in thread
-    thread->fpu_context = (void*)context;
-    
+    if( context == NULL ) return -1;
+
+    // link to thread
+    thread->fpu_context = (void *)context;
     return 0;
-}  // hal_fpu_context_create()
-
-/////////////////////////////////////////////
-error_t hal_fpu_context_copy( thread_t * dst,
-                              thread_t * src )
-{
-    kmem_req_t  req;
-
-    // allocate memory for dst fpu_context
-    req.type   = KMEM_FPU_CTX;
-    req.flags  = AF_KERNEL | AF_ZERO;
-
-    hal_fpu_context_t * dst_context = (hal_fpu_context_t *)kmem_alloc( &req );
-    if( dst_context == NULL ) return ENOMEM;
-
-    // set fpu context pointer in dst thread
-    dst->fpu_context = (void*)dst_context;
-
-    // get fpu context pointer from src thread
+
+}   // end hal_fpu_context_alloc()
+
+//////////////////////////////////////////
+void hal_fpu_context_copy( thread_t * dst,
+                           thread_t * src )
+{
+    assert( (src != NULL) , __FUNCTION__ , "src thread pointer is NULL\n"); 
+    assert( (dst != NULL) , __FUNCTION__ , "dst thread pointer is NULL\n"); 
+
+    // get fpu context pointers
     hal_fpu_context_t * src_context = src->fpu_context;
+    hal_fpu_context_t * dst_context = dst->fpu_context;
 
     // copy CPU context from src to dst
     memcpy( dst_context , src_context , sizeof(hal_fpu_context_t) );
 
-    return 0;
 }  // end hal_fpu_context_copy()
 
@@ -413 +357 @@
 } // end hal_cpu_context_restore()
 
-/////////////////////////////////////
-void hal_fpu_context_dup( xptr_t dst,
-                          xptr_t src )
-{
-        hal_remote_memcpy( dst , src , sizeof(hal_fpu_context_t) );
-}
-
+

trunk/hal/tsar_mips32/core/hal_drivers.c

@@ -49 +49 @@
                            uint32_t   impl )
 {
-        if( impl == IMPL_TXT_TTY )
-        {
-                soclib_tty_init( txt );
-        }
-        else
-        {
-                assert( false , __FUNCTION__ , "undefined TXT device implementation" );
-        }
+        assert( (impl == IMPL_TXT_TTY), __FUNCTION__ , "bad implementation" );
+
+        soclib_tty_init( txt );
 }
 
@@ -67 +62 @@
                            uint32_t   impl )
 {
-    if( impl != IMPL_PIC_SCL )
-    {
-        assert( false , __FUNCTION__ , "undefined PIC device implementation" );
-    }
+    assert( (impl == IMPL_PIC_SCL), __FUNCTION__, "bad implementation" );
 
         soclib_pic_init( pic );
@@ -81 +73 @@
         pic->ext.pic.bind_irq     = &soclib_pic_bind_irq;
         pic->ext.pic.send_ipi     = &soclib_pic_send_ipi;
+        pic->ext.pic.ack_ipi      = &soclib_pic_ack_ipi;
         pic->ext.pic.extend_init  = &soclib_pic_extend_init;
 }
@@ -92 +85 @@
                            uint32_t   impl )
 {
-        if (impl != IMPL_IOB_TSR) 
-        {
-                assert( false , __FUNCTION__ , "undefined IOB device implementation" );
-        }
+        assert( (impl == IMPL_IOB_TSR), __FUNCTION__ , "bad implementation" );
 
         soclib_iob_init( iob );
@@ -138 +128 @@
                            uint32_t   impl )
 {
-    if( impl == IMPL_MMC_TSR )
-    {
-        soclib_mmc_init( mmc );
-    }
-    else
-    {
-        assert( false , __FUNCTION__ , "undefined MMC device implementation" );
-    }
+        assert( (impl == IMPL_MMC_TSR), __FUNCTION__ , "bad implementation" );
+ 
+    soclib_mmc_init( mmc );
 }
 
@@ -156 +141 @@
                            uint32_t   impl )
 {
-    if( impl == IMPL_NIC_SOC )
-    {
-        soclib_nic_init( nic );
-    }
-    else
-    {
-        assert( false , __FUNCTION__ , "undefined NIC device implementation" );
-    }
+        assert( (impl == IMPL_NIC_CBF), __FUNCTION__ , "bad implementation" );
+ 
+    soclib_nic_init( nic );
 }
 
@@ -174 +154 @@
                            uint32_t   impl )
 {
-    if( impl == IMPL_DMA_SCL )
-    {
-        soclib_dma_init( dma );
-    }
-    else
-    {
-        assert( false , __FUNCTION__ , "undefined DMA implementation" );
-    }
+        assert( (impl == IMPL_DMA_SCL), __FUNCTION__ , "bad implementation" );
+ 
+    soclib_dma_init( dma );
 }
 

trunk/hal/tsar_mips32/core/hal_exception.c

@@ -58 +58 @@
 
 //////////////////////////////////////////////////////////////////////////////////////////
-// This enum defines the mask valuesi for an MMU exception code reported by the mips32.
+// This enum defines the mask values for an MMU exception code reported by the mips32.
 //////////////////////////////////////////////////////////////////////////////////////////
 
 typedef enum
 {
-    MMU_EXCP_PAGE_UNMAPPED   = 0x0003,
-    MMU_EXCP_USER_PRIVILEGE  = 0x0004,
-    MMU_EXCP_USER_WRITE      = 0x0008,
-    MMU_EXCP_USER_EXEC       = 0x1010,
+    MMU_WRITE_PT1_UNMAPPED        = 0x0001,
+    MMU_WRITE_PT2_UNMAPPED        = 0x0002,
+    MMU_WRITE_PRIVILEGE_VIOLATION = 0x0004,
+    MMU_WRITE_ACCESS_VIOLATION    = 0x0008,
+    MMU_WRITE_UNDEFINED_XTN       = 0x0020,
+    MMU_WRITE_PT1_ILLEGAL_ACCESS  = 0x0040,
+    MMU_WRITE_PT2_ILLEGAL_ACCESS  = 0x0080,
+    MMU_WRITE_DATA_ILLEGAL_ACCESS = 0x0100,
+
+    MMU_READ_PT1_UNMAPPED         = 0x1001,
+    MMU_READ_PT2_UNMAPPED         = 0x1002,
+    MMU_READ_PRIVILEGE_VIOLATION  = 0x1004,
+    MMU_READ_EXEC_VIOLATION       = 0x1010,
+    MMU_READ_UNDEFINED_XTN        = 0x1020,
+    MMU_READ_PT1_ILLEGAL_ACCESS   = 0x1040,
+    MMU_READ_PT2_ILLEGAL_ACCESS   = 0x1080,
+    MMU_READ_DATA_ILLEGAL_ACCESS  = 0x1100,
 }
 mmu_exception_subtype_t;
@@ -148 +161 @@
     process = this->process;
 
-    excp_dmsg("\n[DMSG] %s : enter for thread %x in process %x / is_ins = %d\n",
-    __FUNCTION__ , this->trdid , process->pid , is_ins );
-
     // get relevant values from MMU
         hal_get_mmu_excp( &mmu_ins_excp_code,
@@ -157 +167 @@
                           &mmu_dat_bad_vaddr );
 
-    excp_dmsg("\n[DMSG] %s : icode = %x / ivaddr = %x / dcode = %x / dvaddr = %x\n",
-    __FUNCTION__ , mmu_ins_excp_code , mmu_ins_bad_vaddr ,
-                   mmu_dat_excp_code , mmu_dat_bad_vaddr );
-
     // get exception code and faulty vaddr, depending on IBE/DBE
     if( is_ins )
@@ -173 +179 @@
     }
 
-    excp_dmsg("\n[DMSG] %s : excp_code = %x / bad_vaddr = %x\n",
-    __FUNCTION__ , excp_code , bad_vaddr );
-
-    // analyse exception code
-    if( excp_code & MMU_EXCP_PAGE_UNMAPPED )
-    {
-        excp_dmsg("\n[DMSG] %s : type PAGE_UNMAPPED\n", __FUNCTION__ );
-
-        // enable IRQs before handling page fault
-        // hal_enable_irq( NULL );
-
-        // try to map the unmapped PTE
-        error = vmm_handle_page_fault( process, 
-                                       bad_vaddr >> CONFIG_PPM_PAGE_SHIFT );  // vpn
-        // disable IRQs
-        // hal_disable_irq( NULL );
-
-        if( error )     // not enough memory
-        {
-            printk("\n[ERROR] in %s for thread %x : cannot map vaddr = %x\n",
-               __FUNCTION__ , this->trdid , bad_vaddr );
-
-                    return EXCP_USER_ERROR;
-        } 
-        else            // page fault successfully handled
-        {
-            excp_dmsg("\n[DMSG] %s : page fault handled / bad_vaddr = %x / excp_code = %x\n",
-                             __FUNCTION__ , bad_vaddr , excp_code );
+ excp_dmsg("\n[DBG] %s : core[%x,%d] / is_ins %d / code %x / vaddr %x\n",
+__FUNCTION__ , local_cxy , this->core->lid , is_ins, excp_code, bad_vaddr );
+
+   // analyse exception code
+    switch( excp_code )
+    {
+        case MMU_WRITE_PT1_UNMAPPED:      // non fatal
+        case MMU_WRITE_PT2_UNMAPPED:
+        case MMU_READ_PT1_UNMAPPED:
+        case MMU_READ_PT2_UNMAPPED:
+        {
+            // try to map the unmapped PTE
+            error = vmm_handle_page_fault( process, 
+                                           bad_vaddr >> CONFIG_PPM_PAGE_SHIFT );  // vpn
+            if( error )   
+            {
+                printk("\n[ERROR] in %s for thread %x : cannot map vaddr = %x\n",
+                __FUNCTION__ , this->trdid , bad_vaddr );
+
+                        return EXCP_USER_ERROR;
+            } 
+            else            // page fault successfull
+            {
+
+excp_dmsg("\n[DBG] %s : core[%x,%d] / page-fault handled for vaddr = %x\n",
+__FUNCTION__ , local_cxy , this->core->lid , bad_vaddr );
   
-            return EXCP_NON_FATAL;
-        }
-    }
-    else if( excp_code & MMU_EXCP_USER_PRIVILEGE )
-    {
-        printk("\n[ERROR] in %s for thread %x : user access to kernel vseg at vaddr = %x\n",
-               __FUNCTION__ , this->trdid , bad_vaddr );
-
-        return EXCP_USER_ERROR;
-    }
-    else if( excp_code & MMU_EXCP_USER_EXEC )
-    {
-        printk("\n[ERROR] in %s for thread %x : access to non-exec vseg at vaddr = %x\n",
-               __FUNCTION__ , this->trdid , bad_vaddr );
-
-        return EXCP_USER_ERROR;
-    }
-    else if( excp_code & MMU_EXCP_USER_WRITE )
-    {
-        printk("\n[ERROR] in %s for thread %x : write to non-writable vseg at vaddr = %x\n",
-               __FUNCTION__ , this->trdid , bad_vaddr );
-
-        return EXCP_USER_ERROR;
-    }
-    else  // this is a kernel error => panic    
-    {
-        printk("\n[PANIC] in %s for thread %x : kernel exception = %x / vaddr = %x\n",
-               __FUNCTION__ , this->trdid , excp_code , bad_vaddr );
-
-        return EXCP_KERNEL_PANIC;
-    }
-  
+                return EXCP_NON_FATAL;
+            }
+        }
+        case MMU_WRITE_PRIVILEGE_VIOLATION:  // illegal access user error
+        case MMU_READ_PRIVILEGE_VIOLATION:
+        {
+            printk("\n[ERROR] in %s for thread %x : illegal user access to vaddr = %x\n",
+            __FUNCTION__ , this->trdid , bad_vaddr );
+
+            return EXCP_USER_ERROR;
+        }
+        case MMU_WRITE_ACCESS_VIOLATION:     // user error or Copy-on-Write
+        {
+            // access page table to get GPT_COW flag
+            bool_t cow = hal_gpt_pte_is_cow( &(process->vmm.gpt),
+                                             bad_vaddr >> CONFIG_PPM_PAGE_SHIFT );  // vpn
+
+            if( cow )                        // Copy-on-Write 
+            {
+                // try to allocate and copy the page
+                error = vmm_copy_on_write( process,
+                                           bad_vaddr >> CONFIG_PPM_PAGE_SHIFT );  // vpn
+                if( error )
+                {
+                    printk("\n[ERROR] in %s for thread %x : cannot cow vaddr = %x\n",
+                    __FUNCTION__ , this->trdid , bad_vaddr );
+
+                            return EXCP_USER_ERROR;
+                }
+                else         // Copy on write successfull
+                {
+
+excp_dmsg("\n[DBG] %s : core[%x,%d] / copy-on-write handled for vaddr = %x\n",
+__FUNCTION__ , local_cxy , this->core->lid , bad_vaddr );
+
+                    return EXCP_NON_FATAL;
+                } 
+            }
+            else                             // non writable user error
+            {
+                printk("\n[ERROR] in %s for thread %x : write to non-writable vaddr = %x\n",
+                __FUNCTION__ , this->trdid , bad_vaddr );
+
+                return EXCP_USER_ERROR;
+            }
+        }
+        case MMU_READ_EXEC_VIOLATION:        // user error
+        {
+            printk("\n[ERROR] in %s for thread %x : read to non-executable vaddr = %x\n",
+            __FUNCTION__ , this->trdid , bad_vaddr );
+
+            return EXCP_USER_ERROR;
+        }
+        default:                             // this is a kernel error => panic    
+        {
+            printk("\n[PANIC] in %s for thread %x : kernel exception = %x / vaddr = %x\n",
+            __FUNCTION__ , this->trdid , excp_code , bad_vaddr );
+
+            return EXCP_KERNEL_PANIC;
+        }
+    }  
 } // end hal_mmu_exception()
 
@@ -242 +275 @@
 // @ this     : pointer on faulty thread descriptor.
 // @ regs_tbl : pointer on register array.
-// @ return always EXCP_NON_FATAL
+// @ error    : EXCP_USER_ERROR or EXCP_KERNEL_PANIC
 //////////////////////////////////////////////////////////////////////////////////////////
 static void hal_exception_dump( thread_t * this,
-                                reg_t    * regs_tbl )
+                                reg_t    * regs_tbl,
+                                error_t    error )
 {
     uint32_t  save_sr;
+    core_t  * core = this->core;
 
     // get pointers on TXT0 chdev
-    xptr_t    txt0_xp  = chdev_dir.txt[0];
+    xptr_t    txt0_xp  = chdev_dir.txt_tx[0];
     cxy_t     txt0_cxy = GET_CXY( txt0_xp );
     chdev_t * txt0_ptr = GET_PTR( txt0_xp );
@@ -260 +295 @@
     remote_spinlock_lock_busy( lock_xp , &save_sr );
 
-    if( this->type == THREAD_USER )
-    nolock_printk("\n================= USER ERROR / cycle %d ====================\n",
-           hal_time_stamp() );
+    if( error == EXCP_USER_ERROR )
+    {
+        nolock_printk("\n========= USER ERROR / core[%x,%d] / cycle %d ==============\n",
+        local_cxy , core->lid , (uint32_t)hal_get_cycles() );
+    }
     else
-    nolock_printk("\n================= KERNEL PANIC / cycle %d ==================\n",
-           hal_time_stamp() );
+    {
+        nolock_printk("\n======= KERNEL PANIC / core[%x,%d] / cycle %d ==============\n",
+        local_cxy , core->lid , (uint32_t)hal_get_cycles() );
+    }
 
         nolock_printk("  thread type = %s / trdid = %x / pid %x / core[%x,%d]\n"
@@ -272 +311 @@
            this->core->lid, this->local_locks, this->remote_locks, this->blocked );
 
-        nolock_printk("CR    %X  EPC   %X  SR    %X  SP     %X\n",
-                   regs_tbl[UZ_CR], regs_tbl[UZ_EPC], regs_tbl[UZ_SR], regs_tbl[UZ_SP]);
-
-    nolock_printk("at_1  %X  v0_2  %X  v1_3  %X  a0_4   %X  a1_5   %X\n",
-               regs_tbl[UZ_AT], regs_tbl[UZ_V0], regs_tbl[UZ_V1], regs_tbl[UZ_A0], regs_tbl[UZ_A1]);
+        nolock_printk("cp0_cr %X   cp0_epc %X   cp0_sr %X   cp2_mode %X\n",
+                   regs_tbl[UZ_CR], regs_tbl[UZ_EPC], regs_tbl[UZ_SR], regs_tbl[UZ_MODE]);
+
+    nolock_printk("at_01 %X  v0_2  %X  v1_3  %X  a0_4   %X  a1_5   %X\n",
+               regs_tbl[UZ_AT],regs_tbl[UZ_V0],regs_tbl[UZ_V1],regs_tbl[UZ_A0],regs_tbl[UZ_A1]);
 
     nolock_printk("a2_6  %X  a3_7  %X  t0_8  %X  t1_9   %X  t2_10  %X\n",
@@ -284 +323 @@
                    regs_tbl[UZ_T3],regs_tbl[UZ_T4],regs_tbl[UZ_T5],regs_tbl[UZ_T6],regs_tbl[UZ_T7]);
 
-    nolock_printk("t8_24 %X  t9_25 %X  gp_28 %X  c0_hi  %X  c0_lo  %X\n",
-                   regs_tbl[UZ_T8],regs_tbl[UZ_T9],regs_tbl[UZ_GP],regs_tbl[UZ_HI],regs_tbl[UZ_LO]);
-
     nolock_printk("s0_16 %X  s1_17 %X  s2_18 %X  s3_19  %X  s4_20  %X\n",
                    regs_tbl[UZ_S0],regs_tbl[UZ_S1],regs_tbl[UZ_S2],regs_tbl[UZ_S3],regs_tbl[UZ_S4]);
   
-    nolock_printk("s5_21 %X  s6_22 %X  s7_23 %X  s8_30  %X  ra_31  %X\n",
-               regs_tbl[UZ_S5],regs_tbl[UZ_S6],regs_tbl[UZ_S7],regs_tbl[UZ_S8],regs_tbl[UZ_RA]);
+    nolock_printk("s5_21 %X  s6_22 %X  s7_23 %X  s8_24  %X  ra_25  %X\n",
+               regs_tbl[UZ_S5],regs_tbl[UZ_S6],regs_tbl[UZ_S7],regs_tbl[UZ_T8],regs_tbl[UZ_T9]);
+
+    nolock_printk("gp_28 %X  sp_29 %X  S8_30 %X  ra_31  %X\n",
+                   regs_tbl[UZ_GP],regs_tbl[UZ_SP],regs_tbl[UZ_S8],regs_tbl[UZ_RA]);
 
     // release the lock
@@ -311 +350 @@
         excCode        = (regs_tbl[UZ_CR] >> 2) & 0xF;
 
-    excp_dmsg("\n[DMSG] %s : enter for thread %x in process %x / xcode = %x / cycle %d\n",
-    __FUNCTION__ , this->trdid , this->process->pid , excCode , hal_time_stamp() );
+excp_dmsg("\n[DBG] %s : core[%x,%d] / thread %x in process %x / xcode %x / cycle %d\n",
+__FUNCTION__, local_cxy, this->core->lid, this->trdid, 
+this->process->pid, excCode, (uint32_t)hal_get_cycle() );
 
         switch(excCode)
@@ -355 +395 @@
         if( error == EXCP_USER_ERROR )          //  user error => kill user process
         {
-        hal_exception_dump( this , regs_tbl );
-        sys_kill( this->process->pid , SIGKILL );
+        hal_exception_dump( this , regs_tbl , error );
+
+        // FIXME : replace this loop by sys_kill()
+        while( 1 ) asm volatile ("nop");
+        // sys_kill( this->process->pid , SIGKILL );
         }
     else if( error == EXCP_KERNEL_PANIC )   // kernel error => kernel panic
     {
-        hal_exception_dump( this , regs_tbl );
+        hal_exception_dump( this , regs_tbl , error );
         hal_core_sleep();
     }
 
-    excp_dmsg("\n[DMSG] %s : exit for thread %x in process %x / cycle %d\n",
-    __FUNCTION__ , this->trdid , this->process->pid , hal_time_stamp() );
+excp_dmsg("\n[DBG] %s : core[%x,%d] exit / thread %x in process %x / cycle %d\n",
+__FUNCTION__, local_cxy, this->core->lid, this->trdid, this->process->pid, hal_time_stamp() );
 
 }  // end hal_do_exception()

trunk/hal/tsar_mips32/core/hal_gpt.c

@@ -135 +135 @@
     uint32_t   attr;
 
-    gpt_dmsg("\n[DMSG] %s : core[%x,%d] enter\n", 
-    __FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid );
+gpt_dmsg("\n[DBG] %s : core[%x,%d] enter\n", 
+__FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid );
 
     // check page size
@@ -157 +157 @@
     // initialize generic page table descriptor
     page_xp   = XPTR( local_cxy , page );
-
         gpt->ptr  = GET_PTR( ppm_page2base( page_xp ) );
         gpt->ppn  = ppm_page2ppn( page_xp );
-        gpt->page = GET_PTR( page_xp );
 
     // identity map the kentry_vseg (must exist for all processes)
@@ -167 +165 @@
          vpn < (CONFIG_VMM_KENTRY_BASE + CONFIG_VMM_KENTRY_SIZE); vpn++ )
     {
-        gpt_dmsg("\n[DMSG] %s : identity map vpn %d\n", __FUNCTION__ , vpn );
+
+gpt_dmsg("\n[DBG] %s : identity map vpn %d\n", __FUNCTION__ , vpn );
 
         error = hal_gpt_set_pte( gpt,
@@ -181 +180 @@
     }
 
-    gpt_dmsg("\n[DMSG] %s : core[%x,%d] exit\n",
-    __FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid );
+gpt_dmsg("\n[DBG] %s : core[%x,%d] exit\n",
+__FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid );
 
         return 0;
@@ -271 +270 @@
 } // end hal_gpt_destroy()
 
-////////////////////////////////
-void hal_gpt_print( gpt_t * gpt,
-                    pid_t   pid )
-{
+///////////////////////////////////////////
+void hal_gpt_display( process_t * process )
+{
+    gpt_t    * gpt;
         uint32_t   ix1;
         uint32_t   ix2;
@@ -285 +284 @@
     vpn_t      vpn;
 
-
+    assert( (process != NULL) , __FUNCTION__ , "NULL process pointer\n");
+
+    // get pointer on gpt
+    gpt = &(process->vmm.gpt);
+
+    // get pointer on PT1 
     pt1 = (uint32_t *)gpt->ptr;
 
     printk("\n***** Generic Page Table for process %x : &gpt = %x / &pt1 = %x\n\n",
-    pid , gpt , pt1 );
+    process->pid , gpt , pt1 );
 
     // scan the PT1
@@ -324 +328 @@
         }
         }
-} // end hal_gpt_print()
+} // end hal_gpt_display()
 
 
@@ -351 +355 @@
     uint32_t            tsar_attr;           // PTE attributes for TSAR MMU
 
-    gpt_dmsg("\n[DMSG] %s : core[%x,%d] enter for vpn = %x / ppn = %x / gpt_attr = %x\n", 
+    gpt_dmsg("\n[DBG] %s : core[%x,%d] enter for vpn = %x / ppn = %x / gpt_attr = %x\n", 
     __FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid , vpn , ppn , attr );
  
@@ -364 +368 @@
     tsar_attr = gpt2tsar( attr );
 
-    gpt_dmsg("\n[DMSG] %s : core[%x,%d] / vpn = %x / &pt1 = %x / tsar_attr = %x\n", 
+    gpt_dmsg("\n[DBG] %s : core[%x,%d] / vpn = %x / &pt1 = %x / tsar_attr = %x\n", 
     __FUNCTION__, local_cxy , CURRENT_THREAD->core->lid , vpn , pt1 , tsar_attr );
 
@@ -396 +400 @@
         pte1 = *pte1_ptr;
         
-        gpt_dmsg("\n[DMSG] %s : core[%x,%d] / vpn = %x / current_pte1 = %x\n", 
+        gpt_dmsg("\n[DBG] %s : core[%x,%d] / vpn = %x / current_pte1 = %x\n", 
         __FUNCTION__, local_cxy , CURRENT_THREAD->core->lid , vpn , pte1 );
         
@@ -438 +442 @@
             pt2     = (uint32_t *)GET_PTR( ppm_ppn2base( pt2_ppn ) );
 
-        gpt_dmsg("\n[DMSG] %s : core[%x,%d] / vpn = %x / pte1 = %x / &pt2 = %x\n", 
+        gpt_dmsg("\n[DBG] %s : core[%x,%d] / vpn = %x / pte1 = %x / &pt2 = %x\n", 
         __FUNCTION__, local_cxy , CURRENT_THREAD->core->lid , vpn , pte1 , pt2 );
         
@@ -450 +454 @@
         hal_fence();
 
-    gpt_dmsg("\n[DMSG] %s : core[%x,%d] exit / vpn = %x / pte2_attr = %x / pte2_ppn = %x\n", 
+    gpt_dmsg("\n[DBG] %s : core[%x,%d] exit / vpn = %x / pte2_attr = %x / pte2_ppn = %x\n", 
     __FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid , vpn , 
     pt2[2 * ix2] , pt2[2 * ix2 + 1] );
@@ -727 +731 @@
 error_t hal_gpt_copy( gpt_t  * dst_gpt,
                       gpt_t  * src_gpt,
+                      vpn_t    vpn_base,
+                      vpn_t    vpn_size,
                       bool_t   cow )
 {
+    vpn_t        vpn;       // current vpn
+
     uint32_t     ix1;       // index in PT1
     uint32_t     ix2;       // index in PT2
@@ -737 +745 @@
     uint32_t   * src_pt2;   // local pointer on PT2 for SRC_GPT
 
-    uint32_t     pte1;
+        kmem_req_t   req;       // for dynamic PT2 allocation
+
+    uint32_t     src_pte1;
+    uint32_t     dst_pte1;
+
     uint32_t     pte2_attr;
     uint32_t     pte2_ppn;
-    uint32_t     pte2_writable;
 
     page_t     * page;
@@ -748 +759 @@
     ppn_t        dst_pt2_ppn;
 
-    // get pointers on PT1 for src_gpt & dst_gpt
+gpt_dmsg("\n[DBG] %s : core[%x,%d] enter\n", 
+__FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid );
+
+    // check page size
+    assert( (CONFIG_PPM_PAGE_SIZE == 4096) , __FUNCTION__ ,
+    "for TSAR, the page must be 4 Kbytes\n" );
+
+    // check SRC_PT1 and DST_PT1 existence
+    assert( (src_gpt->ptr != NULL) , __FUNCTION__ , "SRC_PT1 does not exist\n");
+    assert( (dst_gpt->ptr != NULL) , __FUNCTION__ , "DST_PT1 does not exist\n");
+
+    // get pointers on SRC_PT1 and DST_PT1
     src_pt1 = (uint32_t *)src_gpt->ptr;
     dst_pt1 = (uint32_t *)dst_gpt->ptr;
 
+    // scan pages in vseg
+    for( vpn = vpn_base ; vpn < (vpn_base + vpn_size) ; vpn++ )
+    {
+        ix1 = TSAR_MMU_IX1_FROM_VPN( vpn );
+        ix2 = TSAR_MMU_IX2_FROM_VPN( vpn );
+
+        // get SRC_PT1 entry
+        src_pte1 = src_pt1[ix1];
+
+        // do nothing if SRC_PTE1 unmapped
+                if( (src_pte1 & TSAR_MMU_MAPPED) != 0 )   // SRC_PTE1 is mapped 
+        {
+            assert( (src_pte1 & TSAR_MMU_SMALL) , __FUNCTION__ ,
+            "no BIG page for user process in TSAR architecture\n" );
+
+            // get DST_PT1 entry
+            dst_pte1 = dst_pt1[ix1];
+
+            // map dst_pte1 if required
+            if( (dst_pte1 & TSAR_MMU_MAPPED) == 0 ) 
+            { 
+                // allocate one physical page for a new DST_PT2
+                    req.type  = KMEM_PAGE;
+                    req.size  = 0;                     // 1 small page 
+                    req.flags = AF_KERNEL | AF_ZERO;
+                    page = (page_t *)kmem_alloc( &req );
+
+                if( page == NULL )
+                {
+                                printk("\n[ERROR] in %s : cannot allocate PT2\n", __FUNCTION__ );
+                    return ENOMEM;
+                }
+
+                // build extended pointer on page descriptor
+                page_xp = XPTR( local_cxy , page );
+
+                // get PPN for this new DST_PT2 
+                dst_pt2_ppn    = (ppn_t)ppm_page2ppn( page_xp );
+
+                // build the new dst_pte1
+                dst_pte1 = TSAR_MMU_MAPPED | TSAR_MMU_SMALL | dst_pt2_ppn;
+
+                // register it in DST_GPT
+                dst_pt1[ix1] = dst_pte1;
+            }
+
+            // get PPN and pointer on SRC_PT2
+            src_pt2_ppn = (ppn_t)TSAR_MMU_PTBA_FROM_PTE1( src_pte1 );
+            src_pt2     = (uint32_t *)GET_PTR( ppm_ppn2base( src_pt2_ppn ) );
+
+            // get PPN and pointer on DST_PT2
+            dst_pt2_ppn = (ppn_t)TSAR_MMU_PTBA_FROM_PTE1( dst_pte1 );
+            dst_pt2     = (uint32_t *)GET_PTR( ppm_ppn2base( dst_pt2_ppn ) );
+
+            // get attr and ppn from SRC_PT2
+            pte2_attr = TSAR_MMU_ATTR_FROM_PTE2( src_pt2[2 * ix2] );
+            pte2_ppn  = TSAR_MMU_PPN_FROM_PTE2(  src_pt2[2 * ix2 + 1] );
+
+            // no copy if SRC_PTE2 unmapped
+            if( (pte2_attr & TSAR_MMU_MAPPED) != 0 )  // valid PTE2 in SRC_GPT
+            {
+                // set a new PTE2 in DST_PT2
+                dst_pt2[2*ix2]     = pte2_attr;
+                dst_pt2[2*ix2 + 1] = pte2_ppn;
+                        
+                // FIXME increment page descriptor refcount for the referenced page
+
+                // handle Copy-On-Write 
+                if( cow && (pte2_attr & TSAR_MMU_WRITABLE) )
+                {
+                    // reset WRITABLE flag in DST_GPT
+                    hal_atomic_and( &dst_pt2[2*ix2] , ~TSAR_MMU_WRITABLE );
+
+                    // set COW flag in DST_GPT
+                    hal_atomic_or( &dst_pt2[2*ix2] , TSAR_MMU_COW );
+                }
+            }
+        }   // end if PTE1 mapped
+    }   // end loop on vpn
+
+    hal_fence();
+
+gpt_dmsg("\n[DBG] %s : core[%x,%d] exit\n", 
+__FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid );
+
+    return 0;
+
+}  // end hal_gpt_copy()
+
+///////////////////////////////////////
+bool_t hal_gpt_pte_is_cow( gpt_t * gpt,
+                           vpn_t   vpn )
+{
+    uint32_t * pt1;
+    uint32_t   pte1;
+
+    uint32_t * pt2;
+    ppn_t      pt2_ppn;
+
+    uint32_t   ix1 = TSAR_MMU_IX1_FROM_VPN( vpn );
+    uint32_t   ix2 = TSAR_MMU_IX2_FROM_VPN( vpn );
+
+    // get PTE1 value
+        pt1  = gpt->ptr;
+    pte1 = pt1[ix1];
+
+        if( (pte1 & TSAR_MMU_MAPPED) == 0 )    // PT1 entry not mapped
+        {
+                return false;
+        }
+
+        if( (pte1 & TSAR_MMU_SMALL) == 0 )     // it's a PTE1
+        {
+                return false;
+        }
+    else                                   // it's a PTD1
+    {
+        // compute PT2 base address
+        pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 );
+        pt2     = (uint32_t*)GET_PTR( ppm_ppn2base( pt2_ppn ) );
+
+        if( pt2[2*ix2] & TSAR_MMU_COW ) return true;
+        else                            return false;
+    }
+}   // end hal_gpt_pte_is_cow()
+
+
+
+
+
+
+
+
+
+
+
+
+/* deprecated : old hal_gpt_copy [AG]
+ 
     // scan the SRC_PT1
         for( ix1 = 0 ; ix1 < 2048 ; ix1++ )
@@ -834 +995 @@
 }  // end hal_gpt_copy()
 
+*/

trunk/hal/tsar_mips32/core/hal_interrupt.c

@@ -33 +33 @@
                                reg_t    * regs_tbl ) 
 {
-    irq_dmsg("\n[DMSG] %s : enter / core[%x,%d] / cycle %d\n",
-    __FUNCTION__ , local_cxy , this->core->lid , hal_time_stamp() );
 
-    // access local ICU to call the relevant ISR
+irq_dmsg("\n[DBG] %s : core[%x,%d] enter at cycle %d\n",
+__FUNCTION__ , local_cxy , this->core->lid , hal_time_stamp() );
+
+    // As ALMOS-MKH does not define a generic interrupt handler,
+    // we directly access the local TSAR ICU to call the relevant ISR
     soclib_pic_irq_handler();
-           
-    irq_dmsg("\n[DMSG] %s : exit / core[%x,%d] / cycle %d\n",
-    __FUNCTION__ , local_cxy , this->core->lid , hal_time_stamp() );
+
+irq_dmsg("\n[DBG] %s : core[%x,%d] exit at cycle %d\n",
+__FUNCTION__ , local_cxy , this->core->lid , hal_time_stamp() );
+
 }

trunk/hal/tsar_mips32/core/hal_kentry.S

@@ -189 +189 @@
         mtc0    $3,         $12                         # set new sr
 
-        # signal that core enters kernel
-        la      $1,     cluster_core_kernel_enter
-        jalr    $1
-    nop
-
 #---------------------------------------------------------------------------------------
 # This code call the relevant Interrupt / Exception / Syscall handler,
@@ -241 +236 @@
 # -----------------------------------------------------------------------------------
 kentry_exit:
-
-        # signal that core exit kernel
-    la      $1,     cluster_core_kernel_exit
-    jalr    $1
-    nop
 
         # restore registers from uzone

trunk/hal/tsar_mips32/core/hal_kentry.h

@@ -41 +41 @@
 
 #define      UZ_MODE         0    /* c2_mode */             
-#define      UZ_AT           1
-#define      UZ_V0           2
-#define      UZ_V1           3
-#define      UZ_A0           4 
-#define      UZ_A1           5
-#define      UZ_A2           6
-#define      UZ_A3           7
-#define      UZ_T0           8
-#define      UZ_T1           9
-#define      UZ_T2           10
-#define      UZ_T3           11
-#define      UZ_T4           12
-#define      UZ_T5           13
-#define      UZ_T6           14
-#define      UZ_T7           15
-#define      UZ_T8           16
-#define      UZ_T9           17
-#define      UZ_S0           18
-#define      UZ_S1           19
-#define      UZ_S2           20
-#define      UZ_S3           21
-#define      UZ_S4           22
-#define      UZ_S5           23
-#define      UZ_S6           24
-#define      UZ_S7           25
-#define      UZ_S8           26
-#define      UZ_GP           27
-#define      UZ_RA           28
-#define      UZ_EPC          29   /* c0_epc */
-#define      UZ_CR           30   /* c0_cr */
-#define      UZ_SP           31
-#define      UZ_SR           32   /* c0_sr */
+#define      UZ_AT           1    /* at_01   */
+#define      UZ_V0           2    /* v0_02   */
+#define      UZ_V1           3    /* v1_03   */
+#define      UZ_A0           4    /* a0_04   */
+#define      UZ_A1           5    /* a1_05   */
+#define      UZ_A2           6    /* a2_06   */
+#define      UZ_A3           7    /* a3_07   */
+#define      UZ_T0           8    /* t0_08   */
+#define      UZ_T1           9    /* t1_09   */
+#define      UZ_T2           10   /* t2_10   */
+#define      UZ_T3           11   /* t3_11   */
+#define      UZ_T4           12   /* t4_12   */
+#define      UZ_T5           13   /* t5_13   */
+#define      UZ_T6           14   /* t6_14   */
+#define      UZ_T7           15   /* t7_15   */
+#define      UZ_T8           16   /* t8_24   */
+#define      UZ_T9           17   /* t9_25   */
+#define      UZ_S0           18   /* s0_16   */
+#define      UZ_S1           19   /* s1_17   */
+#define      UZ_S2           20   /* s2_18   */
+#define      UZ_S3           21   /* s3_19   */
+#define      UZ_S4           22   /* s4_20   */
+#define      UZ_S5           23   /* s5_21   */
+#define      UZ_S6           24   /* s6_22   */
+#define      UZ_S7           25   /* s7_23   */
+#define      UZ_S8           26   /* s8_30   */
+#define      UZ_GP           27   /* gp_28   */
+#define      UZ_RA           28   /* ra_31   */
+#define      UZ_EPC          29   /* c0_epc  */
+#define      UZ_CR           30   /* c0_cr   */
+#define      UZ_SP           31   /* sp_29   */
+#define      UZ_SR           32   /* c0_sr   */
 #define      UZ_LO           33
 #define      UZ_HI           34

trunk/hal/tsar_mips32/core/hal_ppm.c

@@ -45 +45 @@
 // kmem memory allocator in the local cluster. This array starts in first free page
 // after kernel code, as defined by the 'offset' field in boot_info.
-//
-// For the TSAR architecture the MIP32 EBASE register defining the kernel entry point
-// fot Interrupts, Exceptions and Syscalls, has to be redefined.
 //////////////////////////////////////////////////////////////////////////////////////////
 
@@ -124 +121 @@
 }  // end hal_ppm_init()
 
-////////////////////////////////////////
-void hal_core_init( boot_info_t * info )
-{
-        // get relevant info from boot_info structure
-        reg_t kentry_base = info->kentry_base;
 
-    // set CP0_EBASE register
-    hal_set_ebase( kentry_base );
-
-}  // end hal_core_init()
-
-

trunk/hal/tsar_mips32/core/hal_special.c

@@ -31 +31 @@
 
 struct thread_s;
-
-/////////////////////////////////
-void hal_set_ebase( reg_t  base )
-{ 
-        asm volatile ("mtc0    %0,  $15,  1" : : "r" (base));
-}
 
 //////////////////////////
@@ -200 +194 @@
 void hal_fence()
 {
-        asm volatile
-        ( "sync    \n":: );
+        asm volatile ("sync");
 }
 
@@ -213 +206 @@
 void hal_core_sleep()
 {
-        asm volatile
-        ("wait   \n"::);
+        asm volatile ("wait");
 }
 
@@ -221 +213 @@
 { 
     asm volatile
-    ( "1:                    \n"
+    ( ".set noreorder        \n"
       "or    $27,  %0,  $0   \n"
+      "1:                    \n"
       "addi  $27, $27,  -1   \n"
+      "nop                   \n"
       "bne   $27,  $0,  1b   \n"
       "nop                   \n"
-      : : "r" (delay) : "$27" );
+      ".set reorder          \n"
+      : : "r" (delay>>2) : "$27" );
 }
 

trunk/hal/tsar_mips32/core/hal_switch.S

@@ -22 +22 @@
  */
 
-#---------------------------------------------------------------------------------
-# This code makes the following assumptions:
+    .section   .switch , "ax" , @progbits
+
+    .global  hal_do_cpu_switch
+    .global  hal_do_cpu_save
+
+    .set     noat 
+    .set     noreorder 
+
+#---------------------------------------------------------------------------------
+# The hal_do_cpu_switch() function makes the following assumptions:
 # - register $4 contains a pointer on the old thread context.
 # - register $5 contains a pointer on the new thread context.
-# When the switch is completed, it jumps to address contained in register $31
-# of the new context.
-#---------------------------------------------------------------------------------
-
-    .section   .switch , "ax" , @progbits
-
-    .ent     hal_do_switch
-    .global  hal_do_switch
-
-    .set     noat 
-    .set     noreorder 
-
-hal_do_switch:
+#---------------------------------------------------------------------------------
+hal_do_cpu_switch:
 
     move    $26,   $4                  /* $26 <= ctx_old */
@@ -133 +130 @@
     mthi    $27                        /* restore hi from slot 26 */
     lw      $27,  27*4($26)         
-    mtlo    $27                        /* restote lo from slot 27 */
+    mtlo    $27                        /* restore lo from slot 27 */
 
         lw      $28,  28*4($26)         
         lw      $29,  29*4($26)         
         lw      $30,  30*4($26)         
-        lw      $31,  31*4($26)         
-
-        lw      $27,  32*4($26)            /* $27 <= c2_ptpr */
+        lw      $31,  31*4($26)            /* restore ra from slot 31 */
+
+        lw      $27,  32*4($26)
         mtc2    $27,  $0                   /* restore c2_ptpr from slot 32 */
 
-        lw      $27,  35*4($26)            /* $27 <= c0_th */      
+        lw      $27,  35*4($26)      
     mtc0        $27,  $4, 2                /* restore c0_th from slot 35 */
 
-        lw      $27,  33*4($26)            /* $27 <= c2_mode */
-        lw      $26,  34*4($26)            /* $26 <= c0_sr */
+        lw      $27,  33*4($26)
+        lw      $26,  34*4($26)
 
         mtc2    $27,  $1                   /* restore c2_mode from slot 33 */
@@ -155 +152 @@
     nop
 
+#---------------------------------------------------------------------------------
+# The hal_do_cpu_save()function makes the following assumptions:
+# - register $4 contains a pointer on the target thread context.
+# - register $5 contains the target thread descriptor pointer.
+# - register $6 contains the offset to add to stack pointer.
+#---------------------------------------------------------------------------------
+hal_do_cpu_save:
+
+    move    $26,  $4                  /* $26 <= context */
+
+    move    $27,  $5
+        sw      $27,  35*4($26)           /* save child thread to slot 35 */
+
+    add     $27,  $6,  $29
+    sw      $27,  29*4($26)           /* save (sp_29 + offset) to slot 29 */
+
+    mfc0    $27,  $12               
+        sw      $27,  34*4($26)           /* save c0_sr to slot 34 */
+
+        mfc2    $27,  $0                
+        sw      $27,  32*4($26)           /* save c2_ptpr to slot 32 */
+
+        mfc2    $27,  $1                
+        sw      $27,  33*4($26)           /* save c2_mode to slot 33 */
+
+    mfc0    $27,   $14              
+    sw      $27,   0*4($26)           /* save c0_epc to slot 0 */
+ 
+    sw      $1,    1*4($26)         
+    sw      $2,    2*4($26)         
+    sw      $3,    3*4($26)         
+    sw      $4,    4*4($26)         
+    sw      $5,    5*4($26)         
+    sw      $6,    6*4($26)         
+    sw      $7,    7*4($26)         
+
+    sw      $8,    8*4($26)         
+    sw      $9,    9*4($26)         
+    sw      $10,  10*4($26)         
+    sw      $11,  11*4($26)         
+    sw      $12,  12*4($26)         
+    sw      $13,  13*4($26)         
+    sw      $14,  14*4($26)         
+    sw      $15,  15*4($26)         
+
+    sw      $16,  16*4($26)         
+    sw      $17,  17*4($26)         
+    sw      $18,  18*4($26)         
+    sw      $19,  19*4($26)         
+    sw      $20,  20*4($26)         
+    sw      $21,  21*4($26)         
+    sw      $22,  22*4($26)         
+    sw      $23,  23*4($26)         
+
+    sw      $24,  24*4($26)         
+    sw      $25,  25*4($26)         
+
+    mfhi    $27                     
+    sw      $27,  26*4($26)           /* save hi to slot 26 */
+
+    mflo    $27                     
+    sw      $27,  27*4($26)           /* save lo to slot 27 */
+
+    sw      $28,  28*4($26)           /* save gp to slot 28 */
+
+    sw      $30,  30*4($26)           /* save s8 to slot 30 */
+    sw      $31,  31*4($26)           /* save ra to slot 31 */
+
+    sync
+
+    jr      $31                       /* return to caller */
+    nop
+
         .set reorder                    
     .set at                         
 
-    .end hal_do_switch
-

trunk/hal/tsar_mips32/core/hal_syscall.c

@@ -26 +26 @@
 #include <do_syscall.h>
 #include <thread.h>
+#include <printk.h>
 #include <hal_kentry.h>
 
@@ -33 +34 @@
                      reg_t    * regs_tbl )
 {
+
+#if(CONFIG_SYSCALL_DEBUG & 0x1)
+printk("\n[DBG] %s : core[%x,%d] enter at cycle %d\n",
+__FUNCTION__ , local_cxy , this->core->lid , hal_time_stamp() );
+#endif
+
         register reg_t      arg0;
         register reg_t      arg1;
@@ -58 +65 @@
         regs_tbl[UZ_V1]   = this->errno;
         regs_tbl[UZ_EPC] += 4;
+
+#if(CONFIG_SYSCALL_DEBUG & 0x1)
+printk("\n[DBG] %s : core[%x,%d] exit at cycle %d\n",
+__FUNCTION__ , local_cxy , this->core->lid , hal_time_stamp() );
+#endif
+
 }

trunk/hal/tsar_mips32/core/hal_types.h

@@ -48 +48 @@
 typedef   signed long long int      int64_t;
 typedef unsigned long long int     uint64_t;
-
-/***************************************************************************
- * Pthread related types 
- **************************************************************************/
-
-typedef uint32_t      pthread_t;               
-typedef uint32_t      pthread_mutexattr_t;
-typedef uint32_t      pthread_barrier_t;
-typedef uint32_t      pthread_barrierattr_t;
-typedef uint32_t      sem_t;
-typedef uint32_t      pthread_cond_t;
-typedef uint32_t      pthread_condattr_t;
-typedef uint32_t      pthread_rwlock_t;
-typedef uint32_t      pthread_rwlockattr_t;
-typedef uint32_t      pthread_key_t;
 
 /***************************************************************************

trunk/hal/tsar_mips32/core/hal_uspace.c

@@ -45 +45 @@
     hal_disable_irq( &save_sr );
 
+
         for( i = 0 ; i < wsize ; i++ )          // transfer one word per iteration
         {
@@ -129 +130 @@
 }  // end hal_copy_to_uspace()
 
-//////////////////////////////////////////
-error_t hal_strcpy_from_uspace( char     * k_dst,
-                                char     * u_src,
-                                uint32_t   max_size )
-
-{
-
-// TODO implement the max_size handling, and error handling
-
-    uint32_t save_sr;
+//////////////////////////////////////////////
+void hal_strcpy_from_uspace( char     * k_dst,
+                             char     * u_src,
+                             uint32_t   size )
+{
+    uint32_t save_sr;
+
     uint32_t src = (uint32_t)u_src;
     uint32_t dst = (uint32_t)k_dst;
-    uint32_t length;
-    error_t error;
-    paddr_t paddr;
-
-    // XXX XXX XXX: must be converted, to handle faults
-    error = vmm_v2p_translate( false , u_src , &paddr );
-    if( error )
-    {
-        return EFAULT;
-    }
-
-    length = hal_strlen_from_uspace( u_src );
-    if( length >= max_size )
-    {
-        return EFAULT;
-    }
-
-    hal_disable_irq( &save_sr );
-
-    // loop on characters while non NUL 
+
+    hal_disable_irq( &save_sr );
+
+    // loop on characters while ( (character != NUL) and (count < size ) 
     asm volatile(
-        "mfc2   $15,   $1           \n"   /* save current MMU_MODE          */
-        "1:                         \n"   /* loop entry                     */
-        "ori    $14,   $0,  0x7     \n"  
-        "mtc2   $14,   $1                       \n"   /* MMU_MODE <= DTLB ON            */
-        "lb         $13,   0(%0)        \n"   /* read char from user space      */
-        "mtc2   $15,   $1                       \n"   /* restore MMU_MODE               */
-            "sb     $13,   0(%1)        \n"   /* store char to kernel space     */
-        "addi   %0,    %0,  1       \n"   /* increment SRC pointer          */
-        "addi   %1,    %1,  1       \n"   /* increment DST pointer          */
-        "bne    $13,   $0,  1b      \n"   /* test NUL                       */
+        ".set noreorder             \n"
+        "move   $11,   %0           \n"   /* $11 <= count == size           */
+        "move   $12,   %1           \n"   /* $12 <= u_src                   */
+        "move   $13,   %2           \n"   /* $13 <= k_dst                   */
+        "mfc2   $15,   $1           \n"   /* $15 <= MMU_MODE                */
+        "ori    $14,   $15,  0x7    \n"   /* $14 <= mode DTLB on            */
+        "1:                         \n"
+        "mtc2   $14,   $1                       \n"   /* MMU_MODE <= DTLB ON            */
+        "lb     $10,   0($12)       \n"   /* read char from user space      */
+        "mtc2   $15,   $1                       \n"   /* restore MMU_MODE               */
+            "sb     $10,   0($13)       \n"   /* store char to kernel space     */
+        "beq    $13,   $0,   2f     \n"   /* exit if char = 0               */
+        "addi   $11,   $11, -1      \n"   /* decrement count                */
+        "addi   $12,   $12,  1      \n"   /* increment u_src pointer        */
+        "beq    $11,   $0,   2f     \n"   /* exit if count == 0             */
+        "addi   $13,   $13,  1      \n"   /* increment k_src pointer        */
+        "j                   1b     \n"   /* jump to next iteration         */
+        "2:                         \n"
         "nop                        \n"
-        : : "r"( src ) , "r"( dst ) : "$13","$14","$15", "memory" );
-
-    hal_restore_irq( save_sr );
-
-    return 0;
+        ".set reorder               \n"
+        : 
+        : "r"(size),"r"(src),"r"(dst)
+        : "$10","$11","$12","$13","$14","$15" );
+        
+    hal_restore_irq( save_sr ); 
+
 } // hal_strcpy_from_uspace()
 
 ////////////////////////////////////////////
-error_t hal_strcpy_to_uspace( char     * u_dst,
-                              char     * k_src,
-                              uint32_t   max_size )
-{
-
-// TODO implement the max_size handling, and error handling
-
-    uint32_t save_sr;
+void hal_strcpy_to_uspace( char     * u_dst,
+                           char     * k_src,
+                           uint32_t   size )
+{
+    uint32_t save_sr;
+
     uint32_t src = (uint32_t)k_src;
     uint32_t dst = (uint32_t)u_dst;
@@ -194 +184 @@
     hal_disable_irq( &save_sr );
 
-    // loop on characters while non NUL 
+    // loop on characters while ( (character != NUL) and (count < size) ) 
     asm volatile(
-        "mfc2   $15,   $1           \n"   /* save current MMU_MODE          */
-        "1:                         \n"   /* loop entry                     */
-        "lb         $13,   0(%0)        \n"   /* read char from kernel space    */
-        "ori    $14,   $0,  0x7     \n"  
-        "mtc2   $14,   $1                       \n"   /* MMU_MODE <= DTLB ON            */
-            "sb     $13,   0(%1)        \n"   /* store char to user space       */
-        "mtc2   $15,   $1                       \n"   /* restore MMU_MODE               */
-        "addi   %0,    %0,  1       \n"   /* increment SRC pointer          */
-        "addi   %1,    %1,  1       \n"   /* increment DST pointer          */
-        "bne    $13,   $0,  1b      \n"   /* test NUL                       */
+        ".set noreorder             \n"
+        "move   $11,   %0           \n"   /* $11 <= count == size           */
+        "move   $12,   %1           \n"   /* $12 <= k_src                   */
+        "move   $13,   %2           \n"   /* $13 <= u_dst                   */
+        "mfc2   $15,   $1           \n"   /* $15 <= MMU_MODE                */
+        "ori    $14,   $15,  0x7    \n"   /* $14 <= mode DTLB on            */
+        "1:                         \n"
+        "lb     $10,   0($12)       \n"   /* read char from kernel space    */
+        "mtc2   $14,   $1                       \n"   /* MMU_MODE <= DTLB ON            */
+            "sb     $10,   0($13)       \n"   /* store char to user space       */
+        "mtc2   $15,   $1                       \n"   /* restore MMU_MODE               */
+        "beq    $13,   $0,   2f     \n"   /* exit if char == 0              */
+        "addi   $11,   $11, -1      \n"   /* decrement count                */
+        "addi   $12,   $12,  1      \n"   /* increment k_src pointer        */
+        "beq    $11,   $0,   2f     \n"   /* exit if count == size          */
+        "addi   $13,   $13,  1      \n"   /* increment u_src pointer        */
+        "j                   1b     \n"   /* jump to next iteration         */
+        "2:                         \n"
         "nop                        \n"
-        : : "r"( src ) , "r"( dst ) : "$13","$14","$15", "memory" );
-
-    hal_restore_irq( save_sr );
-
-    return 0;
+        ".set reorder               \n"
+        :
+        : "r"(size),"r"(src),"r"(dst)
+        : "$10","$11","$12","$13","$14","$15" );
+        
+    hal_restore_irq( save_sr ); 
+
 } // hal_strcpy_to_uspace()
 
@@ -218 +218 @@
 {
     uint32_t save_sr;
-    uint32_t str      = (uint32_t)u_str;
-    uint32_t count    = 0;
+    uint32_t count = 0;
+
+    uint32_t str = (uint32_t)u_str;
 
     hal_disable_irq( &save_sr ); 
 
         asm volatile(
-        "ori    $15,   %0,   0      \n"   /* $15 <= count                   */
+        ".set noreorder             \n"
         "ori    $13,   %1,   0      \n"   /* $13 <= str                     */
-    
-        "mfc2   $15,   $1           \n"   /* save   MMU_MODE                */
-        "ori    $14,   $0,   0x7    \n"   /* $14 <= mode DTLB on            */
-        "mtc2   $14,   $1                       \n"   /* MMU_MODE <= DTLB ON            */
-
+        "mfc2   $15,   $1           \n"   /* $15 <= MMU_MODE                */
+        "ori    $14,   $15,  0x7    \n"   /* $14 <= mode DTLB on            */
+        "mtc2   $14,   $1                       \n"   /* MMU_MODE <= DTLB ON            */
         "1:                         \n"
-        "lb         $13,   0(%0)        \n"   /* read char from kernel space    */
+        "lb         $12,   0($13)       \n"   /* read char from user space      */
         "addi   $13,   $13,  1      \n"   /* increment address              */
-        "bne    $13,   $0,   1b     \n"   /* loop until NUL found           */
-        "addi   $15,   $15,  1      \n"   /* increment counter              */
-
-        "mtc2   $14,   $1                       \n"   /* restore MMU_MODE               */
-        : "+r"(count) : "r"(str) : "$13","$14","$15" );
+        "bne    $12,   $0,   1b     \n"   /* loop until NUL found           */
+        "addi   %0,    %0,   1      \n"   /* increment count                */
+        "mtc2   $15,   $1                       \n"   /* restore MMU_MODE               */
+        ".set reorder               \n"
+        : "+r"(count) 
+        : "r"(str) 
+        : "$12","$13","$14","$15" );
 
     hal_restore_irq( save_sr );

trunk/hal/tsar_mips32/drivers/soclib_bdv.c

@@ -104 +104 @@
 
     // waiting policy  depends on the command type
+    // - for IOC_READ / IOC_WRITE commands, this function is called by the server thread
+    // - for IOC_SYNC_READ command, this function is directly called by the client thread
 
-    if( cmd_type == IOC_SYNC_READ )                  // polling policy
+    if( cmd_type == IOC_SYNC_READ )                   // status polling policy
     {
         uint32_t status;
@@ -131 +133 @@
     { 
         thread_block( CURRENT_THREAD , THREAD_BLOCKED_DEV_ISR );
-        sched_yield( NULL );
+        sched_yield();
+
+        // the IO operation status is reported in the command by the ISR
     }
     

trunk/hal/tsar_mips32/drivers/soclib_dma.c

@@ -91 +91 @@
     // Block and deschedule server thread
     thread_block( CURRENT_THREAD , THREAD_BLOCKED_DEV_ISR );
-    sched_yield( NULL );
+    sched_yield();
     
 } // soclib_dma_cmd()

trunk/hal/tsar_mips32/drivers/soclib_hba.c

@@ -197 +197 @@
             else                                // retry if asynchronous access.
             {
-                sched_yield( NULL );
+                sched_yield();
             }
         }
@@ -240 +240 @@
     {
         thread_block( CURRENT_THREAD , THREAD_BLOCKED_DEV_ISR );
-        sched_yield( NULL );
+        sched_yield();
     }
             

trunk/hal/tsar_mips32/drivers/soclib_pic.c

@@ -43 +43 @@
 extern  lapic_input_t  lapic_input;  // defined in dev_pic.h / allocated in kernel_init.c
  
+
+
 //////////////////////////////////////////////////////////////////////////////////////
 //        SOCLIB PIC private functions 
@@ -127 +129 @@
                            &pti_status );
 
-    irq_dmsg("\n[DMSG] %s : enter for core[%x,%d] / WTI = %x / HWI = %x / WTI = %x\n",
+    irq_dmsg("\n[DBG] %s : core[%x,%d] enter / WTI = %x / HWI = %x / WTI = %x\n",
              __FUNCTION__ , local_cxy , core->lid , wti_status , hwi_status , pti_status );
 
@@ -140 +142 @@
             assert( (index == core->lid) , __FUNCTION__ , "illegal IPI index" );
 
-            irq_dmsg("\n[DMSG] %s : core[%x,%d] received an IPI / cycle %d\n",
+            irq_dmsg("\n[DBG] %s : core[%x,%d] received an IPI / cycle %d\n",
              __FUNCTION__ , local_cxy , core->lid , hal_time_stamp() );
 
@@ -168 +170 @@
             else                                 // call relevant ISR
             {
-                irq_dmsg("\n[DMSG] %s : core[%x,%d] received external WTI %d / cycle %d\n",
+                irq_dmsg("\n[DBG] %s : core[%x,%d] received external WTI %d / cycle %d\n",
                 __FUNCTION__ , local_cxy , core->lid , index , hal_time_stamp() );
 
@@ -196 +198 @@
         else                    // call relevant ISR
         {
-            irq_dmsg("\n[DMSG] %s : core[%x,%d] received HWI %d / cycle %d\n",
+            irq_dmsg("\n[DBG] %s : core[%x,%d] received HWI %d / cycle %d\n",
             __FUNCTION__ , local_cxy , core->lid , index , hal_time_stamp() );
 
@@ -208 +210 @@
         index = pti_status - 1;
 
-        irq_dmsg("\n[DMSG] %s : core[%x,%d] received PTI %d / cycle %d\n",
+        irq_dmsg("\n[DBG] %s : core[%x,%d] received PTI %d / cycle %d\n",
         __FUNCTION__ , core->lid , local_cxy , index , hal_time_stamp() );
 
@@ -248 +250 @@
     uint32_t * iopic_seg_ptr = (uint32_t *)GET_PTR( pic->base );
 
-    // reset the IOPIC component registers : mask all input IRQs
+    // reset the IOPIC component registers : disable all input IRQs
     for( i = 0 ; i < CONFIG_MAX_EXTERNAL_IRQS ; i++ )
     {
@@ -364 +366 @@
     {
         // get external IRQ index
-        uint32_t  irq_id;   
-        if     (  func == DEV_FUNC_IOC            ) irq_id = iopic_input.ioc[channel];
-        else if(  func == DEV_FUNC_TXT            ) irq_id = iopic_input.txt[channel];
-        else if( (func == DEV_FUNC_NIC) &&  is_rx ) irq_id = iopic_input.nic_rx[channel];
-        else if( (func == DEV_FUNC_NIC) && !is_rx ) irq_id = iopic_input.nic_tx[channel];
-        else if(  func == DEV_FUNC_IOB            ) irq_id = iopic_input.iob;
+        uint32_t  hwi_id;   
+        if     (  func == DEV_FUNC_IOC            ) hwi_id = iopic_input.ioc[channel];
+        else if(  func == DEV_FUNC_TXT  &&  is_rx ) hwi_id = iopic_input.txt_rx[channel];
+        else if(  func == DEV_FUNC_TXT  && !is_rx ) hwi_id = iopic_input.txt_tx[channel];
+        else if( (func == DEV_FUNC_NIC) &&  is_rx ) hwi_id = iopic_input.nic_rx[channel];
+        else if( (func == DEV_FUNC_NIC) && !is_rx ) hwi_id = iopic_input.nic_tx[channel];
+        else if(  func == DEV_FUNC_IOB            ) hwi_id = iopic_input.iob;
         else      assert( false , __FUNCTION__ , "illegal device functionnal type\n");
 
@@ -385 +388 @@
         uint32_t lsb_wdata = (uint32_t)wti_xp;
         uint32_t msb_wdata = (uint32_t)(wti_xp >> 32);
-        xptr_t   lsb_xp = XPTR( seg_pic_cxy , seg_pic_ptr+irq_id*IOPIC_SPAN+IOPIC_ADDRESS );
-        xptr_t   msb_xp = XPTR( seg_pic_cxy , seg_pic_ptr+irq_id*IOPIC_SPAN+IOPIC_EXTEND );
+        xptr_t   lsb_xp = XPTR( seg_pic_cxy , seg_pic_ptr+hwi_id*IOPIC_SPAN+IOPIC_ADDRESS );
+        xptr_t   msb_xp = XPTR( seg_pic_cxy , seg_pic_ptr+hwi_id*IOPIC_SPAN+IOPIC_EXTEND );
         hal_remote_sw( lsb_xp , lsb_wdata );
         hal_remote_sw( msb_xp , msb_wdata );
 
-        // unmask IRQ in IOPIC
-        hal_remote_sw( XPTR( seg_pic_cxy , seg_pic_ptr+irq_id*IOPIC_SPAN+IOPIC_MASK ), 1 );
+        // enable IRQ in IOPIC
+        hal_remote_sw( XPTR( seg_pic_cxy , seg_pic_ptr+hwi_id*IOPIC_SPAN+IOPIC_MASK ), 1 );
 
         // update the WTI interrupt vector for core[lid]
         core_t * core = &LOCAL_CLUSTER->core_tbl[lid];
         ((soclib_pic_core_t *)core->pic_extend)->wti_vector[wti_id] = src_chdev;
+
+pic_dmsg("\n[DBG] %s : %s / channel = %d / rx = %d / hwi_id = %d / wti_id = %d / cluster = %x\n",
+__FUNCTION__ , chdev_func_str( func ) , channel , is_rx , hwi_id , wti_id , local_cxy );
+
     }
     else if( (func == DEV_FUNC_DMA) || (func == DEV_FUNC_MMC) )   // internal IRQ => HWI
@@ -411 +418 @@
         core_t * core = &LOCAL_CLUSTER->core_tbl[lid];
         ((soclib_pic_core_t *)core->pic_extend)->wti_vector[hwi_id] = src_chdev;
+
+pic_dmsg("\n[DBG] %s : %s / channel = %d / hwi_id = %d / cluster = %x\n",
+__FUNCTION__ , chdev_func_str( func ) , channel , hwi_id , local_cxy );
+
     }
     else
@@ -494 +505 @@
 
     // set period value in XCU (in cycles)
-    uint32_t cycles = period * SOCLIB_CYCLES_PER_MS * CONFIG_SCHED_TICK_MS_PERIOD;
+    uint32_t cycles = period * SOCLIB_CYCLES_PER_MS;
     base[(XCU_PTI_PER << 5) | lid] = cycles;
 
@@ -525 +536 @@
 }
 
-
-
+/////////////////////////
+void soclib_pic_ack_ipi()
+{
+    // get calling core local index
+    lid_t      lid  = CURRENT_THREAD->core->lid;
+
+    // get pointer on local XCU segment base
+    uint32_t * base = soclib_pic_xcu_base();
+
+    // acknowlege IPI
+    uint32_t   ack  = base[(XCU_WTI_REG << 5) | lid];
+
+    // we must make a fake use for ack value to avoid a warning
+    if( (ack + 1) == 0 ) panic("this should never happen");
+}
+    
+

trunk/hal/tsar_mips32/drivers/soclib_pic.h

@@ -1 +1 @@
 /*
- * soclib_pic.c - soclib PIC driver definition.
+ * soclib_pic.h - soclib PIC driver definition.
  *
  * Author  Alain Greiner (2016,2017)
@@ -90 +90 @@
 #define SOCLIB_MAX_PTI         16 
 
-#define SOCLIB_CYCLES_PER_MS   1000    // for a SystemC virtual prototype 
+#define SOCLIB_CYCLES_PER_MS   60    // SystemC virtual prototype at 60 KHz
 
 /******************************************************************************************
@@ -238 +238 @@
 
 /******************************************************************************************
- * This function activates the WTI[lid] in the local cluster, wherehe lid is the calling
+ * This function activates the WTI[lid] in the local cluster, where lid is the calling
  * core local index.
  *****************************************************************************************/
@@ -252 +252 @@
 void soclib_pic_send_ipi( cxy_t    cxy,
                           lid_t    lid );
+
+/******************************************************************************************
+ * This function acknowleges the WTI[lid] in the local cluster, where lid is the calling
+ * core local index.
+ *****************************************************************************************/
+void soclib_pic_ack_ipi();
 
 

trunk/hal/tsar_mips32/drivers/soclib_tty.c

@@ -27 +27 @@
 #include <remote_spinlock.h>
 #include <thread.h>
+#include <printk.h>
 #include <hal_special.h>
+
+#if CONFIG_READ_DEBUG
+extern uint32_t  enter_tty_cmd;
+extern uint32_t  exit_tty_cmd;
+
+extern uint32_t  enter_tty_isr;
+extern uint32_t  exit_tty_isr;
+#endif
 
 ///////////////////////////////////////
 void soclib_tty_init( chdev_t * chdev )
 {
+    xptr_t reg_xp;
+
     chdev->cmd = &soclib_tty_cmd;
     chdev->isr = &soclib_tty_isr;
-
-    // get extended pointer on TTY-SOCLIB peripheral base address
-    xptr_t tty_xp = chdev->base;
+    chdev->aux = &soclib_tty_aux;
+
+    // get TTY channel and extended pointer on TTY peripheral base address
+    xptr_t   tty_xp  = chdev->base;
+    uint32_t channel = chdev->channel;
 
     // get SOCLIB_TTY device cluster and local pointer
@@ -42 +55 @@
     uint32_t * tty_ptr = (uint32_t *)GET_PTR( tty_xp );
 
-    // mask both TTY_RX_IRQ and TTY_TX_IRQ
-    hal_remote_sw( XPTR( tty_cxy , tty_ptr + TTY_CONFIG_REG ) , 0 );
+    // reset TTY_RX_IRQ_ENABLE 
+    reg_xp = XPTR( tty_cxy , tty_ptr + (channel * TTY_SPAN) + TTY_RX_IRQ_ENABLE );
+    hal_remote_sw( reg_xp , 0 );
+
+    // reset TTY_TX_IRQ_ENABLE
+    reg_xp = XPTR( tty_cxy , tty_ptr + (channel * TTY_SPAN) + TTY_TX_IRQ_ENABLE );
+    hal_remote_sw( reg_xp , 0 );
 }
 
@@ -49 +67 @@
 void __attribute__ ((noinline)) soclib_tty_cmd( xptr_t th_xp )
 {
+
+#if CONFIG_READ_DEBUG
+enter_tty_cmd = hal_time_stamp();
+#endif
+
+txt_dmsg("\n[DBG] %s : core[%x,%d] / DEV thread enter / cycle %d\n", 
+__FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid , hal_time_stamp() );
+
     // get client thread cluster and local pointer
     cxy_t      th_cxy = GET_CXY( th_xp );
@@ -57 +83 @@
     xptr_t   dev_xp = (xptr_t)hal_remote_lwd( XPTR( th_cxy , &th_ptr->txt_cmd.dev_xp ) );
 
+    assert( (type == TXT_READ) || (type == TXT_WRITE) , __FUNCTION__, "illegal command type");
+
     // get TXT device cluster and local pointer
     cxy_t     dev_cxy = GET_CXY( dev_xp );
@@ -72 +100 @@
     uint32_t * base    = tty_ptr + TTY_SPAN * channel;
 
-    if( type == TXT_READ )              // descheduling strategy for calling thread
+    // compute extended pointer on relevant TTY register
+    xptr_t reg_xp; 
+    if( type == TXT_READ )  reg_xp = XPTR( tty_cxy , base + TTY_RX_IRQ_ENABLE );
+    else                    reg_xp = XPTR( tty_cxy , base + TTY_TX_IRQ_ENABLE );
+
+    // enable relevant IRQ : data transfer will be done by the TTY_RX ISR)
+    hal_remote_sw( reg_xp , 1 );
+
+txt_dmsg("\n[DBG] %s : core[%x,%d] DEV thread deschedule / cycle %d\n",
+__FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid , hal_time_stamp() );
+
+    // Block and deschedule server thread
+    thread_block( CURRENT_THREAD , THREAD_BLOCKED_DEV_ISR );
+    sched_yield();
+
+txt_dmsg("\n[DBG] %s : core[%x,%d] / DEV thread resume / cycle %d\n",
+__FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid , hal_time_stamp() );
+
+#if CONFIG_READ_DEBUG
+exit_tty_cmd = hal_time_stamp();
+#endif
+
+}  // end soclib_tty_cmd()
+
+/////////////////////////////////////////////////////////////
+void __attribute__ ((noinline)) soclib_tty_aux( void * args )
+{
+    uint32_t   status;
+    bool_t     empty;
+    uint32_t   i;
+
+    xptr_t     dev_xp = ((txt_aux_t *)args)->dev_xp;
+    char     * buffer = ((txt_aux_t *)args)->buffer;
+    uint32_t   count  = ((txt_aux_t *)args)->count;
+    
+    // get TXT0 chdev cluster and local pointer
+    cxy_t     dev_cxy = GET_CXY( dev_xp );
+    chdev_t * dev_ptr = (chdev_t *)GET_PTR( dev_xp );
+
+    // get extended pointer on TTY channel base address
+    xptr_t tty_xp = (xptr_t)hal_remote_lwd( XPTR( dev_cxy , &dev_ptr->base ) );
+
+    // get TTY channel segment cluster and local pointer
+    cxy_t      tty_cxy = GET_CXY( tty_xp );
+    uint32_t * tty_ptr = (uint32_t *)GET_PTR( tty_xp );
+
+    // get extended pointers on TTY_WRITE & TTY_STATUS registers
+    xptr_t write_xp  = XPTR( tty_cxy , tty_ptr + TTY_WRITE );
+    xptr_t status_xp = XPTR( tty_cxy , tty_ptr + TTY_STATUS );
+
+    // loop on characters (busy waiting strategy)
+    for( i = 0 ; i < count ; i++ )
     {
-        // unmask RX_IRQ (data transfer will be done by the TTY_RX ISR)
-        xptr_t config_xp = XPTR( tty_cxy , base + TTY_CONFIG_REG );
-        uint32_t old = hal_remote_lw( config_xp );
-        uint32_t new = old | TTY_CONFIG_RX_ENABLE;
-        hal_remote_atomic_cas( config_xp , old , new );
-
-        // Block and deschedule server thread
-        thread_block( CURRENT_THREAD , THREAD_BLOCKED_DEV_ISR );
-        sched_yield( NULL );
+        do
+        {
+            // get TTY_STATUS
+            status = hal_remote_lw( status_xp );
+            empty  = ( (status & TTY_STATUS_TX_FULL) == 0 );
+
+            // transfer one byte if TX buffer empty
+            if ( empty )  hal_remote_sb( write_xp , buffer[i] );
+        }
+        while ( empty == false );
     }
-    else if( type == TXT_WRITE )        // descheduling strategy for calling thread
-    {
-        // unmask TX_IRQ (data transfer will be done by the TTY_TX ISR)
-        xptr_t config_xp = XPTR( tty_cxy , base + TTY_CONFIG_REG );
-        uint32_t old = hal_remote_lw( config_xp );
-        uint32_t new = old | TTY_CONFIG_TX_ENABLE;
-        hal_remote_atomic_cas( config_xp , old , new );
-
-        // Block and deschedule server thread
-        thread_block( CURRENT_THREAD , THREAD_BLOCKED_DEV_ISR );
-        sched_yield( NULL );
-    }
-    else if( type == TXT_SYNC_WRITE )  // busy waiting strategy for calling thread
-    {
-        uint32_t   status;
-        bool_t     empty;
-        uint32_t   i;
-
-        // get source buffer extended pointer & bytes count
-        uint32_t count  = hal_remote_lw ( XPTR( th_cxy , &th_ptr->txt_cmd.count ) );
-        xptr_t   buf_xp = hal_remote_lwd( XPTR( th_cxy , &th_ptr->txt_cmd.buf_xp ) );
-
-        // loop on characters
-        for( i = 0 ; i < count ; i++ )
-        {
-            do
-            {
-                // get TTY_STATUS_REG
-                status = hal_remote_lw( XPTR( tty_cxy , base + TTY_STATUS_REG ) );
-                empty  = ( (status & TTY_STATUS_TX_FULL) == 0 );
-
-                if ( empty )  // TTY_TX empty => transfer one byte
-                {
-                    // get one byte from command buffer in client cluster
-                    char byte = (char)hal_remote_lb( buf_xp + i );
-
-                    // write byte to TTY_WRITE_REG in TTY cluster
-                    hal_remote_sb( XPTR( tty_cxy , base + TTY_WRITE_REG ) , byte );
-                }
-            }
-            while ( empty == false );
-        }
-    }
-}  // end soclib_tty_cmd()
+}  // end soclib_tty_aux()
 
 
@@ -135 +172 @@
     uint32_t   type;         // command type
     uint32_t   count;        // number of bytes in buffer
-    xptr_t     buf_xp;       // Rextended pointer on buffer
+    xptr_t     buf_xp;       // extended pointer on buffer
+    xptr_t     status_xp;    // extended pointer on TTY_STATUS register
+    xptr_t     write_xp;     // extended pointer on TTY_WRITE register
+    xptr_t     read_xp;      // extended pointer on TTY_READ register
     uint32_t   status;       // TTY terminal status
     char       byte;         // read byte
     uint32_t   i;
+
+#if CONFIG_READ_DEBUG
+enter_tty_isr = hal_time_stamp();
+#endif
 
     // get extended pointer on client thread
@@ -153 +197 @@
     buf_xp  = hal_remote_lwd( XPTR( client_cxy , &client_ptr->txt_cmd.buf_xp ) );
 
+txt_dmsg("\n[DBG] %s : core[%x,%d] enter / cycle %d\n", 
+__FUNCTION__ , local_cxy, CURRENT_THREAD->core->lid , hal_time_stamp() );
+
     // get SOCLIB_TTY peripheral cluster and local pointer
     cxy_t      tty_cxy = GET_CXY( chdev->base );
@@ -160 +207 @@
     uint32_t * base = tty_ptr + TTY_SPAN * chdev->channel;
 
+    // get extended pointer on TTY registers
+    status_xp = XPTR( tty_cxy , base + TTY_STATUS );
+    write_xp  = XPTR( tty_cxy , base + TTY_WRITE );
+    read_xp   = XPTR( tty_cxy , base + TTY_READ );
+
     if( type == TXT_READ )              // read one single character
     {
-        // get TTY_STATUS_REG
-        status = hal_remote_lw( XPTR( tty_cxy , base + TTY_STATUS_REG ) );
-
-        if( status & TTY_STATUS_RX_FULL )   // TTY_RX full => transfer one byte
-        {
-            // get a byte from TTY_READ_REG, and acknowledge RX_IRQ
-            byte = (char)hal_remote_lb( XPTR( tty_cxy , base + TTY_READ_REG ) );
+        // get TTY_STATUS
+        status = hal_remote_lw( status_xp );
+
+        if( status & TTY_STATUS_RX_FULL )   // TTY_RX full => move one byte
+        {
+            // get a byte from TTY_READ, and acknowledge RX_IRQ
+            byte = (char)hal_remote_lb( read_xp );
 
             // write it to command buffer
             hal_remote_sb( buf_xp , byte );
-
-            // update TTY_WRITE_REG if echo mode
-            if( CONFIG_TXT_ECHO_MODE )
-            {
-                if( (byte == '\b') || (byte == 0x7F) )
-                        {
-                                hal_remote_sb( XPTR( tty_cxy , base + TTY_WRITE_REG ) , '\b' );
-                                hal_remote_sb( XPTR( tty_cxy , base + TTY_WRITE_REG ) , ' '  );
-                                hal_remote_sb( XPTR( tty_cxy , base + TTY_WRITE_REG ) , '\b' );
-                        }
-                else
-                {
-                                hal_remote_sw( XPTR( tty_cxy , base + TTY_WRITE_REG ) , byte );
-                        }
-            }
         }
         else                               // buffer empty => exit ISR for retry
@@ -192 +229 @@
             return;
         }
+
+        // disable RX_IRQ 
+        xptr_t reg_xp = XPTR( tty_cxy , base + TTY_RX_IRQ_ENABLE );
+        hal_remote_sw( reg_xp , 0 );
     }
-    else if( type == TXT_WRITE )         // write a string
+    else if( type == TXT_WRITE )         // write all characters in string
     {
         // loop on characters
         for( i = 0 ; i < count ; i++ )
         {
-            // get TTY_STATUS_REG
-            status = hal_remote_lw( XPTR( tty_cxy , base + TTY_STATUS_REG ) );
-
-            if( (status & TTY_STATUS_TX_FULL) == 0 ) // TTY_TX empty => transfer one byte
+            // get TTY_STATUS
+            status = hal_remote_lw( status_xp );
+
+            if( (status & TTY_STATUS_TX_FULL) == 0 ) // TTY_TX empty => move one byte
             {
                 // get one byte from command buffer
                 byte = (char)hal_remote_lb( buf_xp + i );
 
-                // write byte to TTY_WRITE_REG, and acknowledge TX_IRQ
-                hal_remote_sb( XPTR( tty_cxy , base + TTY_STATUS_REG ) , byte );
+                // write byte to TTY_WRITE, and acknowledge TX_IRQ
+                hal_remote_sb( write_xp , byte );
             }
             else         // TTY_TX full => update command arguments and exit ISR for retry
@@ -216 +257 @@
             }
         }
+
+        // disable TX_IRQ 
+        xptr_t reg_xp = XPTR( tty_cxy , base + TTY_TX_IRQ_ENABLE );
+        hal_remote_sw( reg_xp , 0 );
     }
 
     // The I/O operation completed when we reach this point
-
-    // mask both TTY_RX_IRQ and TTY_TX_IRQ
-    hal_remote_sw( XPTR( tty_cxy , base + TTY_CONFIG_REG ) , 0 );
 
     // set I/O operation status in command
@@ -227 +269 @@
 
     // unblock server thread
-    thread_unblock( XPTR( local_cxy , &chdev->server ) , THREAD_BLOCKED_DEV_ISR );
+    thread_unblock( XPTR( local_cxy , chdev->server ) , THREAD_BLOCKED_DEV_ISR );
 
     // unblock client thread
     thread_unblock( client_xp , THREAD_BLOCKED_IO );
 
+    hal_fence();
+
+txt_dmsg("\n[DBG] %s : core[%x,%d] exit / cycle %d\n", 
+__FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid , hal_time_stamp() );
+
+#if CONFIG_READ_DEBUG
+exit_tty_isr = hal_time_stamp();
+#endif
+
 }  // end soclib_tty_isr()
 

trunk/hal/tsar_mips32/drivers/soclib_tty.h

@@ -38 +38 @@
  ***************************************************************************************/
 
-#define TTY_WRITE_REG          0
-#define TTY_STATUS_REG         1
-#define TTY_READ_REG           2
-#define TTY_CONFIG_REG         3
+#define TTY_WRITE              0
+#define TTY_STATUS             1
+#define TTY_READ               2
+#define TTY_RX_IRQ_ENABLE      3
+#define TTY_TX_IRQ_ENABLE      4
 
-#define TTY_SPAN               4       // number of registers per channel
+#define TTY_SPAN               8       // number of registers per channel
 
 /****************************************************************************************
@@ -51 +52 @@
 #define TTY_STATUS_RX_FULL     1       // TTY_READ_REG full if 1
 #define TTY_STATUS_TX_FULL     2       // TTY_WRITE_REG full if 1
-
-/****************************************************************************************
- * masks for TTY_CONFIG_REG
- ***************************************************************************************/
-
-#define TTY_CONFIG_RX_ENABLE   1       // TTY_RX IRQ enabled if 1
-#define TTY_CONFIG_TX_ENABLE   2       // TTY_TX IRQ enabled if 1
 
 /****************************************************************************************
@@ -68 +62 @@
 
 /****************************************************************************************
- * This function handles the command registered in the thread descriptor identified
- * by the <xp_thread> argument.
- * - For the TXT_READ and TXT_WRITE commands, it only unmask the proper TTY_RX / TTY_TX
- *   IRQ, and blocks the TXT device server thread on the THREAD_BLOCKED_DEV_ISR, as the
- *   data transfer is done by the ISR.
- * - For the TXT_SYNC_READ command, that should be only used by the kernel do display
- *   log or debug messages, it directly access the SOCLIB_TTY registers, using
- *   a busy waiting policy if required.
- ****************************************************************************************
+ * This function implements the TXT_READ & TXT_WRITE commands registered in the client
+ * thread descriptor (in the txt_cmd field), identified by the <xp_thread> argument.
+ * Depending on the command type, it only unmasks the relevant TTY_RX / TTY_TX IRQ,
+ * and blocks the TXT device server thread on the THREAD_BLOCKED_DEV_ISR, as the data
+ * transfer is done by the ISR.
+ * ****************************************************************************************
  * @ thread_xp : extended pointer on client thread descriptor.
  ***************************************************************************************/
 void soclib_tty_cmd( xptr_t thread_xp );
+
+/****************************************************************************************
+ * This function implements the TXT_SYNC_WRITE command registered in the txt_aux_t
+ * structure, using a busy waiting policy, without using the TTY IRQ.
+ * It is used by the kernel do display debug messages on TXT0 terminal, without
+ * interference with another TXT access to another terminal done by the same thread.
+ ****************************************************************************************
+ * @ thread_xp : pointer on the txt_aux_t structure containing the arguments.
+ ***************************************************************************************/
+void soclib_tty_aux( void * args );
 
 /****************************************************************************************