- Timestamp:
- Jul 5, 2018, 3:45:43 PM (6 years ago)
- Location:
- trunk/hal/tsar_mips32/drivers
- Files:
-
- 13 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/hal/tsar_mips32/drivers/soclib_bdv.c
r440 r451 22 22 */ 23 23 24 #include <soclib_bdv.h> 25 #include <hal_kernel_types.h> 24 26 #include <chdev.h> 25 27 #include <dev_ioc.h> 26 #include <soclib_bdv.h>27 28 #include <printk.h> 28 29 #include <thread.h> 29 30 #include <spinlock.h> 30 31 31 32 32 /////////////////////////////////////// -
trunk/hal/tsar_mips32/drivers/soclib_bdv.h
r437 r451 26 26 27 27 #include <chdev.h> 28 #include <hal_ types.h>28 #include <hal_kernel_types.h> 29 29 30 30 /******************************************************************************************** -
trunk/hal/tsar_mips32/drivers/soclib_dma.c
r436 r451 22 22 */ 23 23 24 #include <hal_ types.h>24 #include <hal_kernel_types.h> 25 25 #include <chdev.h> 26 26 #include <dev_dma.h> -
trunk/hal/tsar_mips32/drivers/soclib_hba.h
r437 r451 26 26 27 27 #include <chdev.h> 28 #include <hal_ types.h>28 #include <hal_kernel_types.h> 29 29 30 30 /***************************************************************************************** -
trunk/hal/tsar_mips32/drivers/soclib_iob.c
r75 r451 23 23 24 24 #include <kernel_config.h> 25 #include <hal_ types.h>25 #include <hal_kernel_types.h> 26 26 #include <hal_remote.h> 27 27 #include <soclib_iob.h> -
trunk/hal/tsar_mips32/drivers/soclib_iob.h
r75 r451 25 25 #define _SOCLIB_IOB_H_ 26 26 27 #include <hal_ types.h>27 #include <hal_kernel_types.h> 28 28 #include <chdev.h> 29 29 -
trunk/hal/tsar_mips32/drivers/soclib_mmc.c
r440 r451 23 23 24 24 25 #include <hal_ types.h>25 #include <hal_kernel_types.h> 26 26 #include <chdev.h> 27 27 #include <dev_mmc.h> -
trunk/hal/tsar_mips32/drivers/soclib_mmc.h
r75 r451 27 27 #include <chdev.h> 28 28 #include <dev_mmc.h> 29 #include <hal_ types.h>29 #include <hal_kernel_types.h> 30 30 31 31 /******************************************************************************************** -
trunk/hal/tsar_mips32/drivers/soclib_nic.c
r432 r451 22 22 */ 23 23 24 #include <hal_ types.h>24 #include <hal_kernel_types.h> 25 25 #include <hal_remote.h> 26 26 #include <hal_special.h> -
trunk/hal/tsar_mips32/drivers/soclib_nic.h
r75 r451 26 26 27 27 #include <chdev.h> 28 #include <hal_ types.h>28 #include <hal_kernel_types.h> 29 29 30 30 /******************************************************************************************** -
trunk/hal/tsar_mips32/drivers/soclib_pic.c
r440 r451 22 22 */ 23 23 24 #include <hal_ types.h>24 #include <hal_kernel_types.h> 25 25 #include <chdev.h> 26 26 #include <soclib_pic.h> … … 255 255 { 256 256 uint32_t i; // for loop on IOPIC inputs 257 uint32_t x; // for loop on clusters in a row258 uint32_t y; // for loop on clusters in a column inputs259 uint32_t lid; // for loop on cores in a cluster260 261 // get target architecture parameters262 cluster_t * cluster = LOCAL_CLUSTER;263 uint32_t x_size = cluster->x_size;264 uint32_t y_size = cluster->y_size;265 uint32_t y_width = cluster->y_width;266 uint32_t ncores = cluster->cores_nr;267 257 268 258 // get IOPIC controller cluster and segment base pointer 269 cxy_t iopic_seg_cxy = (cxy_t)GET_CXY( pic->base );270 uint32_t * iopic_seg_ptr = (uint32_t *)GET_PTR( pic->base );259 cxy_t iopic_seg_cxy = GET_CXY( pic->base ); 260 uint32_t * iopic_seg_ptr = GET_PTR( pic->base ); 271 261 272 262 // reset the IOPIC component registers : disable all input IRQs … … 277 267 hal_remote_sw( iopic_seg_xp , 0 ); 278 268 } 279 280 // GET XCU controller segment base 281 uint32_t * base = soclib_pic_xcu_base(); 282 283 // reset the XCU component registers in all clusters: 284 // mask all HWIs, all WTIs, and all PTIs, for all cores 285 for( x = 0 ; x < x_size ; x++ ) 286 { 287 for( y = 0 ; y < y_size ; y++ ) 288 { 289 for( lid = 0 ; lid < ncores ; lid++ ) 290 { 291 cxy_t cxy = (x<<y_width) + y; 292 xptr_t hwi_mask_xp = XPTR( cxy , base + (XCU_MSK_HWI_DISABLE << 5 | lid) ); 293 xptr_t wti_mask_xp = XPTR( cxy , base + (XCU_MSK_WTI_DISABLE << 5 | lid) ); 294 xptr_t pti_mask_xp = XPTR( cxy , base + (XCU_MSK_PTI_DISABLE << 5 | lid) ); 295 hal_remote_sw( hwi_mask_xp , 0xFFFFFFFF ); 296 hal_remote_sw( wti_mask_xp , 0xFFFFFFFF ); 297 hal_remote_sw( pti_mask_xp , 0xFFFFFFFF ); 298 } 299 } 300 } 269 301 270 } // end soclib_pic_init() 302 271 … … 357 326 // register PIC extension in cluster manager 358 327 cluster->pic_extend = cluster_ext_ptr; 328 329 // reset the XCU component registers 330 // mask all HWIs, all WTIs, and all PTIs, for all cores in local cluster 331 for( lid = 0 ; lid < cluster->cores_nr ; lid++ ) 332 { 333 xcu_base[XCU_MSK_HWI_DISABLE << 5 | lid] = 0xFFFFFFFF; 334 xcu_base[XCU_MSK_WTI_DISABLE << 5 | lid] = 0xFFFFFFFF; 335 xcu_base[XCU_MSK_PTI_DISABLE << 5 | lid] = 0xFFFFFFFF; 336 } 359 337 360 338 } // end soclib_pic_extend_init() -
trunk/hal/tsar_mips32/drivers/soclib_pic.h
r432 r451 25 25 #define _SOCLIB_PIC_H_ 26 26 27 #include <hal_ types.h>27 #include <hal_kernel_types.h> 28 28 29 29 /**** Forward declarations ****/ … … 167 167 168 168 /****************************************************************************************** 169 * This blocking function disables all input IRQs in the IOPIC controller, and 170 * disables all HWIs, WTIs, and PTIs in the XCU (LAPIC) controllers, for all cores, 171 * in all clusters. 169 * This function disables all input IRQs in the external IOPIC controller. 172 170 * It must be called by a thread running in the cluster containing the PIC chdev. 173 171 ****************************************************************************************** … … 177 175 178 176 /***************************************************************************************** 179 * This function allocates memory from local cluster for the SOCLIBPIC core extensions177 * This function allocates memory from local cluster for the local PIC core extensions 180 178 * of all cores contained in the cluster, initializes the two HWI, WTI interrupt vectors 181 179 * as empty, and registers - for each core - the pointer in core descriptor. 182 * Then it allocates memory from local cluster for the SOCLIB PIC cluster extension, 183 * to implement the XCU WTI allocator, and registers the pointer in cluster manager. 184 * It access the local XCU component to get actual number of HWI / WTI / PTI. 180 * Then it allocates memory from local cluster for the PIC cluster extension, 181 * and registers the pointer in cluster manager. 182 * It accesses the local XCU component to get actual number of HWI / WTI / PTI. 183 * Finally, it disables all HWI/WTI/PTI interrupts for all cores by writing in the 184 * relevant mask registers of the local XCU component. 185 185 ***************************************************************************************** 186 186 * @ xcu_base : local pointer on XCU controller segment base. -
trunk/hal/tsar_mips32/drivers/soclib_tty.c
r446 r451 2 2 * soclib_tty.c - soclib tty driver implementation. 3 3 * 4 * Author Alain Greiner (2016 )4 * Author Alain Greiner (2016,2017,2018) 5 5 * 6 6 * Copyright (c) UPMC Sorbonne Universites … … 22 22 */ 23 23 24 25 #include <hal_kernel_types.h> 24 26 #include <dev_txt.h> 25 27 #include <chdev.h> … … 123 125 #endif 124 126 125 #if DEBUG_HAL_TXT_RX126 uint32_t rx_cycle = (uint32_t)hal_get_cycles();127 if( (DEBUG_HAL_TXT_RX < rx_cycle) && (type == TXT_READ) )128 printk("\n[DBG] %s : thread %x enter for RX / cycle %d\n",129 __FUNCTION__ , CURRENT_THREAD , rx_cycle );130 #endif131 132 #if DEBUG_HAL_TXT_TX133 uint32_t tx_cycle = (uint32_t)hal_get_cycles();134 if( (DEBUG_HAL_TXT_TX < tx_cycle) && (type == TXT_WRITE) )135 printk("\n[DBG] %s : thread %x enter for TX / cycle %d\n",136 __FUNCTION__ , CURRENT_THREAD , tx_cycle );137 #endif138 139 127 // get TXT device cluster and pointers 140 128 xptr_t dev_xp = (xptr_t)hal_remote_lwd( XPTR( th_cxy , &th_ptr->txt_cmd.dev_xp ) ); … … 165 153 byte = hal_remote_lb( buf_xp + done ); 166 154 155 #if DEBUG_HAL_TXT_TX 156 uint32_t tx_cycle = (uint32_t)hal_get_cycles(); 157 if( DEBUG_HAL_TXT_TX < tx_cycle ) 158 printk("\n[DBG] %s : thread %x put character <%c> to TXT%d_TX fifo / cycle %d\n", 159 __FUNCTION__, CURRENT_THREAD, byte, channel, tx_cycle ); 160 #endif 167 161 // write byte to FIFO 168 162 fifo->data[fifo->ptw] = byte; … … 208 202 char byte = fifo->data[fifo->ptr]; 209 203 204 #if DEBUG_HAL_TXT_RX 205 uint32_t rx_cycle = (uint32_t)hal_get_cycles(); 206 if( DEBUG_HAL_TXT_RX < rx_cycle ) 207 printk("\n[DBG] %s : thread %x get character <%c> from TXT%d_RX fifo / cycle %d\n", 208 __FUNCTION__, CURRENT_THREAD, byte, channel, rx_cycle ); 209 #endif 210 210 // update FIFO state 211 211 fifo->ptr = (fifo->ptr + 1) % TTY_FIFO_DEPTH; … … 235 235 assert( false , __FUNCTION__ , "illegal TXT command\n" ); 236 236 } 237 238 #if DEBUG_HAL_TXT_RX239 rx_cycle = (uint32_t)hal_get_cycles();240 if( (DEBUG_HAL_TXT_RX < rx_cycle) && (type == TXT_READ) )241 printk("\n[DBG] %s : thread %x exit after RX / cycle %d\n",242 __FUNCTION__ , CURRENT_THREAD , rx_cycle );243 #endif244 245 #if DEBUG_HAL_TXT_TX246 tx_cycle = (uint32_t)hal_get_cycles();247 if( (DEBUG_HAL_TXT_TX < tx_cycle) && (type == TXT_WRITE) )248 printk("\n[DBG] %s : thread %x exit after TX / cycle %d\n",249 __FUNCTION__ , CURRENT_THREAD , tx_cycle );250 #endif251 237 252 238 #if (DEBUG_SYS_READ & 1) … … 453 439 #if DEBUG_HAL_TXT_RX 454 440 if( DEBUG_HAL_TXT_RX < rx_cycle ) 455 printk("\n[DBG] %s : read character %c from TXT%d\n", __FUNCTION__, byte, channel ); 441 printk("\n[DBG] %s : put character <%c> to TXT%d_RX fifo\n", 442 __FUNCTION__, byte, channel ); 456 443 #endif 457 444 // store byte into FIFO … … 496 483 #if DEBUG_HAL_TXT_TX 497 484 if( DEBUG_HAL_TXT_TX < tx_cycle ) 498 printk("\n[DBG] %s : write character %c to TXT%d\n", __FUNCTION__, byte, channel ); 485 printk("\n[DBG] %s : get character <%c> from TXT%d_TX fifo\n", 486 __FUNCTION__, byte, channel ); 499 487 #endif 500 488 // update TX_FIFO state
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