source: anr-2010/section-3.2.tex @ 349

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1% les objectifs scientifiques/techniques du projet.
2The design steps are presented figure~\ref{coach-flow}.
3\begin{figure}[hbtp]\leavevmode\center
4  \includegraphics[width=.8\linewidth]{flow}
5  \caption{\label{coach-flow} COACH design flow}
6\end{figure}
7\begin{description}
8\item[HPC setup:] During this step, the user splits the application into 2 parts: the host application
9which remains on the PC and the SoC application which is mapped on the FPGA.
10COACH will provide a complete simulation model of the whole system (PC+communication+FPGA-SoC)
11which will allow performance evaluation.
12\item[SoC design:] In this phase,
13COACH will allow the user to obtain virtual prototypes for the SoC at different abstraction levels.
14The user input will consist of a process network describing the coarse grain parallelism
15of the application, an instance of a generic hardware platform
16and a mapping of processes on the platform components.
17COACH will offer different targets to map the processes: 
18software (the process runs as a software task on a SoC processor),
19ASIP (the process runs as a software task on a SoC processor enhanced with dedicated instructions),
20and hardware (the process is implemented as a synthesized hardware coprocessor).
21\item[Application compilation:] Once the SoC architecture is validated through performances
22analysis, COACH will generate automatically an executable containing the host application and
23the FPGA bitstream. This bitstream contains
24both the hardware architecture and the SoC application software.
25The user will be able to launch the application by
26loading the bitstream on an FPGA and running the executable on PC.
27\end{description}
28 
29% l'avancee scientifique attendue. Preciser l'originalite et le caractere
30% ambitieux du projet.
31%FIXME == {NON ceci n'est pas une contribution scientifique. A re-ecrire}
32
33%The main scientific contribution of the project is to unify various synthesis techniques
34%(same input and output formats) allowing the user to swap without engineering effort
35%from one to another and even to chain them. For instance, it will be possible to run loop transformations before synthesis.
36%Another advantage of this framework is to provide different abstraction levels from
37%a single description.
38%Finally, this description is device family independent and its hardware implementation
39%is automatically generated.
40
41% Detailler les verrous scientifiques et techniques a lever par la realisation du projet.
42Hardware/Software co-design is a very complex task. To simplify it, COACH will address the
43following scientific and technological barriers:
44\begin{description}
45\item[\textit{Design Space Exploration by Virtual Prototyping}]:
46        The COACH environment will allow to easily map a parallel application (formally described as
47        an abstract network of process and communication channels) 
48        COACH will permit the system designer to explore the design space, and to define the best
49        hardware/software partitioning of the application.
50\item[\textit{Integration of system level modeling and HLS tools}]:
51        COACH will support the automated generation of hardware accelerators when required
52        by using High-Level Synthesis (HLS) tools. These HLS tools will be
53        fully integrated into a complete system-level design environment.
54        Moreover, COACH will support both data and control dominated applications,
55        and the HLS tools of COACH will support a common language and coding style
56        to avoid re-engineering by the designer.
57        COACH will provide a tool which will automatically explore the micro-architectural
58        design space of coprocessor.
59\item[\textit{High-level code transformation}]:
60        COACH will allow to optimize the memory usage, to enhance the parallelism through
61        loop transformations and parallelization. The challenge is to identify the coarse
62        grained parallelism and to generate,
63        from a sequential algorithm, application containing multiple communicating
64        tasks. COACH will adapt techniques which were developed in the 1990 for
65        the construction of distributed programs. However, in the context of HLS, there are
66        several original problems to be solved, related to the  FIFO communication channels and with
67        memory optimization.
68        COACH will support code transformation by providing a source to source C2C tool.
69\item[\textit{Unified Hardware/Software communication middleware}]:
70        COACH will rely on he SoCLib experience to implement an unified hardware/software communication
71        infrastructure and communication APIs (Application Programming Interface), to support 
72        communications between software tasks running on embedded processors and dedicated
73        hardware coprocessors. The main issue here is to support easy migration
74        from a software implementation to an hardware implementation.
75\item[\textit{Processor customization}]:
76        ASIP (Application Specific Instruction Processor) design will be addressed by the COACH project.
77        COACH will allow system designers to explore the various level of interactions between
78        the original CPU micro-architecture and its extension. It will also allow to retarget
79        the compiler instruction-selection pass. Finally, COACH will integrate ASIP synthesis
80        in a complete System-level design framework.
81\end{description}
82
83%Presenter les resultats escomptes en proposant si possible des criteres de reussite
84%et d'evaluation adaptes au type de projet, permettant d'evaluer les resultats en
85%fin de projet.
86The main result is the framework. It is composed concretely of:
87a communication middleware for HPC,
885 HAS tools (control dominated HLS, data dominated HLS, Coarse grained HLS,
89Memory optimisation HLS and ASIP),
903 architectural templates that are synthesizable and that can be prototyped,
91one design space exploration tool,
922 operating systems (DNA/OS and MUTEKH).
93\\
94The framework fonctionality will be demonstrated with the demonstrators
95(see task-7 page~\pageref{task-7}) and the tutorial example (see task-8
96page~\ref{subtask-tutorial}).
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