Changeset 272 for anr/section-3.2.tex
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- Feb 20, 2010, 5:00:49 PM (14 years ago)
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anr/section-3.2.tex
r269 r272 44 44 \begin{description} 45 45 \item[\textit{Design Space Exploration by Virtual Prototyping}]: 46 The COACH environment will allow to easily map a parallel application described as a process 47 network Model of Computation (MoC) on a shared-memory, MPSoC architecture. COACH will 48 permit to explore the design space by allowing system designer to select and 49 parameterize the target architecture, and to define the best hardware/software 50 partitioning of the application. 51 \item[\textit{High-Level Synthesis}]: 52 COACH will allow the automatic generation of hardware accelerators when required 46 The COACH environment will allow to easily map a parallel application (formally described as 47 an abstract network of process and communication channels) 48 COACH will permit the system designer to explore the design space, and to define the best 49 hardware/software partitioning of the application. 50 \item[\textit{Integration of system level modeling and HLS tools}]: 51 COACH will support the automated generation of hardware accelerators when required 53 52 by using High-Level Synthesis (HLS) tools. These HLS tools will be 54 53 fully integrated into a complete system-level design environment. 55 54 Moreover, COACH will support both data and control dominated applications, 56 and the HLS tools of COACH will support a common language and coding style55 and the HLS tools of COACH will support a common language and coding style 57 56 to avoid re-engineering by the designer. 58 COACH will provide a tool which will automatically explore the micro-architectural57 COACH will provide a tool which will automatically explore the micro-architectural 59 58 design space of coprocessor. 60 59 \item[\textit{High-level code transformation}]: 61 COACH will allow to optimize the memory usage, to enhance the parallelism through60 COACH will allow to optimize the memory usage, to enhance the parallelism through 62 61 loop transformations and parallelization. The challenge is to identify the coarse 63 62 grained parallelism and to generate, 64 63 from a sequential algorithm, application containing multiple communicating 65 tasks. To this aim, one mayadapt techniques which were developed in the 1990 for64 tasks. COACH will adapt techniques which were developed in the 1990 for 66 65 the construction of distributed programs. However, in the context of HLS, there are 67 still several original problems to be solved, mainly to do with the construction of 68 FIFO communication channels and with memory optimization. 69 Additionnal preprocessing, source-level transformations, are thus 70 required to improve the process. 71 Particularly, this includes parallelism exposure and efficient memory mapping. 66 several original problems to be solved, related to the FIFO communication channels and with 67 memory optimization. 72 68 COACH will support code transformation by providing a source to source C2C tool. 73 \item[\textit{Hardware/Software communication middleware}]: 74 COACH will implement an homogeneous HW/SW communication infrastructure and 75 communication APIs (Application Programming Interface), that will be used for 76 communications between software tasks running on embedded processors and 77 dedicated hardware coprocessors. This will allow explore the design space by 78 mapping the tasks of the application (described as a process network) on a 79 shared-memory, MPSoC architecture. 69 \item[\textit{Unified Hardware/Software communication middleware}]: 70 COACH will rely on he SoCLib experience to implement an unified hardware/software communication 71 infrastructure and communication APIs (Application Programming Interface), to support 72 communications between software tasks running on embedded processors and dedicated 73 hardware coprocessors. The main issue here is to support easy migration 74 from a software implementation to an hardware implementation. 80 75 \item[\textit{Processor customization}]: 81 ASIP design will be addressed by the COACH project. COACH will allow system designers to explore 82 the various level of interactions between the original CPU micro-architecture and its 83 extension. It will also allow to retarget the compiler instruction-selection pass. Finally, 84 COACH will integrate ASIP design in a complete System-level design framework. 76 ASIP (Application Specific Instruction Processor) design will be addressed by the COACH project. 77 COACH will allow system designers to explore the various level of interactions between 78 the original CPU micro-architecture and its extension. It will also allow to retarget 79 the compiler instruction-selection pass. Finally, COACH will integrate ASIP synthesis 80 in a complete System-level design framework. 85 81 \end{description} 86 82
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