source: anr-2010/section-5.tex @ 385

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1\subsection{Dissemination}
2
3The COACH project will bring new scientific results in various fields, such as high level synthesis,
4hardware/software codesign, virtual prototyping, hardware oriented compilation techniques,
5automatic parallelisation, etc. These results will be published in relevant International
6Conferences, namely DATE, DAC, or ICCAD.
7
8More generally, the COACH infrastructure and the design flow supported by the COACH
9tools and libraries will be promoted by proposing tutorials on FPGA oriented system level synthesis
10in various worshops and conferences (DATE, DAC, CODES+ISSS...).
11
12Several COACH partners being members of the HiPEAC European Network of Excellence
13(High Performance and Embedded Architecture and Compilation), courses will be proposed for the
14HiPEAC summer school on Advanced Computer Architecture and Compilation for Embedded Systems.
15
16Following the general policy of the SoCLib platform, the COACH project will be an
17open infrastructure, and the COACH tools and libraries will be available in the framework
18of the SoCLib WEB server. This server will be maintened by the UPMC/LIP6 laboratory.
19
20\subsection{Exploitation of results}
21
22The main goal of the COACH project is to help SMEs (Small and Medium Enterprises)
23to enter the world of MPSoC technologies. For small companies, the cost is a primary concern.
24Moreover, these companies have not always in-home expertise in hardware design and VHDL modelling.
25As the fabrication costs of an ASIC is generally too high for SMEs, the COACH project focus
26on FPGA technologies. Regarding the design tools, the cost of advanced ESL (Electronic System Design)
27tools is an issue, and the COACH project will follow the same general policy as the SoCLib platform :
28
29\begin{itemize}
30\item
31All software tools supporting the COACH design flow will be available as free software.
32All academic partners contributing to the COACH project agreed to distribute the ESL software
33tools under the same GPL license as the SoCLib tools. 
34\item
35The SystemC simulation models for the hardware components
36used by the SoCLib architectural template will be distributed as free software
37under a non-contaminant LGPL license.
38\item
39The synthesizable VHDL models supporting the neutral architectural template
40(corresponding to the SocLib IP cores library), will have two modes of dissemination.
41A typical MPSoC contains not only dedicated, synthesized coprocessors. It contains
42also general purpose, reusable components, such as processor cores, memory controllers
43optimised cache controllers, peripheral controllers, or bus controllers.
44For non commercial use (i.e. research or education in an academic context, 
45or feasbility study in an industrial context), the synthesizable VHDL models will be freely available.
46For commercial use, commercial licenses will be negociated between the owners and the customers.
47\item
48The proprietary \altera, \xilinx and \zied IP core libraries are commercial products
49that are not involved by the free software policy, but these libraries will be supported by the
50synthesis tools developped in the COACH project.
51\end{itemize}
52
53This general approach is supported by a large number (\letterOfInterestNb) of SMEs, as
54demonstrated by the "letters of interest" that have been collected during the preparation
55of the project and presented in annexe~\ref{lettre-soutien}.
56
57\subsection{Indusrial Interest in COACH}
58
59\subsubsection*{Partner: \textit{\bull}}
60The team of \bull participating to the COACH project is from the Server Development
61Department who is in charge of developing hardware for open servers (e.g. NovaScale) and
62HPC solutions. The main expectation from COACH is to derive a new component (fine-grain
63FPGA parallelism) to add to existing Bull HPC solutions.
64
65\subsubsection*{Partner: \textit{\xilinx}}
66Computing power potential of our FPGA architectures
67growing very quickly on one side, and complexity of designs implemented
68using our FPGAs dramatically increasing on the other side, it is very
69interesting for us to get high level design methodologies progressing
70quickly and targetting our FPGAs in the most possible efficient way.
71\parlf
72\xilinx goal is to get COACH to generate bitstream optimized as much as possible for
73\xilinx FPGAs in order to both, validate the methodology on our FPGA families, and ease
74future work of our customers.
75
76\subsubsection*{Partner: \textit{\thales}}
77\noindent
78\thales has two main reasons to use the COACH platform:
79\begin{itemize}
80  \item The huge increase of the complexity of the systems in particular by their
81  heterogeneity, raises the issues of design cost and time in the same proportion. The
82  divisions need a design tool which supports the implementation of the applications from
83  algorithm description to the executable code on platforms composed of several general
84  purpose processors and dedicated IPs.
85  \item The applications are more and more complex and adaptable to the environment which
86  leads to a mixture of control aspects and data stream computing aspects. A new approach
87  is necessary to be able to describe this type of application and manage the high level
88  synthesis of system embedding control and data flow aspects.
89\end{itemize}
90\parlf
91TRT (Thales Research and Technology) has the mission to assess and de-risk the emerging
92technologies in its domains of expertise. Specifically in COACH, the studied technology is
93a method and associated tools to make the bridge between application capture at system
94level and the implementation on heterogeneous distributed computing architectures. The
95main stake for Thales behind this is the future design process that will be applied to its
96system teams in the future for the computation-intensive sensor applications. In a context
97of very instable market of tools for parallel programming, it is important to experiment
98and demonstrate the candidate technologies.
99\\
100In its role of internal dissemination, TRT will make the demonstration of the full design
101flow within Thales, and will keep available a platform to later evaluate additional
102applications coming from the Business Units.
103\\
104The COACH platform will be used in the new \thales products in which the algorithms are more
105and more dependent of the environment and have to permanently adapt their behavior in
106varying environments. The target markets are the critical infrastructures security and
107border monitoring.
108
109\subsubsection*{Partner: \textit{\zied}}
110
111\zied is developing a new architecture for embedded system. Our interest in using COACH
112are:
113\begin{itemize}
114  \item firstly, to validate our new architecture by emulating it with COACH.
115  \item Secondly, to use this emulator and the COACH potential to quickly setup
116  demonstrator to our customer.
117\end{itemize}
118
119\subsubsection*{Partner: \textit{\navtel}}
120\navtel has a platform for high performence computation based on ARM processor and FPGAs
121that embedde coprocessors. Currently, the coprocessors are handmade and their designs
122constitute an important part of our product cost. We have try free HLS tools to diminish
123them but the quality of the generated designs was not sufficient to be useable.
124So our interest in COACH is mainly the HLS tools.
125
126\subsubsection*{Industrial supports}
127The following SMEs demonstrate interest to the COACH project (see the "letters of
128interest" in annexe~\ref{lettre-soutien}) and will follow the COACH evolution and will
129evaluate it:
130\letterOfInterest{ALTERA Corporation}{lettres/Altera1.pdf},
131\letterOfInterestPlus{lettres/Altera2.pdf}
132\letterOfInterest{ADACSYS}{lettres/Coach_ADACSYS_lettre_interet},
133\letterOfInterest{MAGILLEM Design Services}{lettres/Coach_lettre_interet_MDS},
134\letterOfInterest{INPIXAL}{lettres/inpixal.jpg},
135\letterOfInterest{CAMKA System}{lettres/CAMKA-System.pdf},
136\letterOfInterest{ATEME}{lettres/ATEME.pdf},
137\letterOfInterest{ALSIM Simulateur}{lettres/Alsim.pdf},
138\letterOfInterest{SILICOMP-AQL}{lettres/itlabs.pdf},
139\letterOfInterest{ABOUND Logic}{lettres/abound.pdf},
140\letterOfInterest{EADS-ASTRIUM}{lettres/Astrium1.pdf}.
141\letterOfInterestPlus{lettres/Astrium2.pdf}
142
143\letterOfInterestClose
144
145\subsection{Management of Intellectual Property}
146A global consortium agreement will be defined during the first six monts of the project.
147As already stated, the COACH project has been prepared during one year by a monthly meeting
148involving the five academic partners. The general free software policy described in the
149previous section has been agreed by academic partners  and has been
150approved by all industrial participants. This free software policy will
151simplify the definition of the consortium agreement.
152
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