source: anr/section-5.tex @ 283

\subsection{Dissemination}

The COACH project will bring new scientific results in various fields, such as high level synthesis,
hardware/software codesign, virtual prototyping, hardware oriented compilation techniques,
automatic parallelisation, etc. These results will be published in relevant International
Conferences, namely DATE, DAC, or ICCAD. 

More generally, the COACH infrastructure and the design flow supported by the COACH
tools and libraries will be promoted by proposing tutorials on FPGA oriented system level synthesis
in various worshops and conferences (DATE, DAC, CODES+ISSS...).

Several COACH partners being members of the HiPEAC European Network of Excellence 
(High Performance and Embedded Architecture and Compilation), courses will be proposed for the
HiPEAC summer school on Advanced Computer Architecture and Compilation for Embedded Systems.

Following the general policy of the SoCLib platform, the COACH project will be an 
open infrastructure, and the COACH tools and libraries will be available in the framework 
of the SoCLib WEB server. This server will be maintened by the UPMC/LIP6 laboratory. 

\subsection{Exploitation of results}

The main goal of the COACH project is to help SMEs (Small and Medium Enterprises) 
to enter the world of MPSoC technologies. For small companies, the cost is a primary concern.
Moreover, these companies have not always in-home expertise in hardware design and VHDL modelling.
As the fabrication costs of an ASIC is generally too high for SMEs, the COACH project focus
on FPGA technologies. Regarding the design tools, the cost of advanced ESL (Electronic System Design) 
tools is an issue, and the COACH project will follow the same general policy as the SoCLib platform :

\begin{itemize}
\item
All software tools supporting the COACH design flow will be available as free software.
All academic partners contributing to the COACH project agreed to distribute the ESL software
tools under the same GPL license as the SoCLib tools.  
\item
The SystemC simulation models for the hardware components
used by the SoCLib architectural template will be distributed as free software 
under a non-contaminant LGPL license.
\item
The synthesizable VHDL models supporting the neutral architectural template
(corresponding to the SocLib IP cores library), will have two modes of dissemination.
A typical MPSoC contains not only dedicated, synthesized coprocessors. It contains
also general purpose, reusable components, such as processor cores, memory controllers
optimised cache controllers, peripheral controllers, or bus controllers.
For non commercial use (i.e. research or education in an academic context,  
or feasibility study in an industrial context), the synthesizable VHDL models will be freely available.
For commercial use, commercial licenses will be negotiated between the owners and the customers.
\item
The proprietary \altera and \xilinx IP core libraries are commercial products
that are not involved by the free software policy, but these libraries will be supported by the 
synthesis tools developed in the COACH project.
\end{itemize}

This general approach is supported by a large number (\letterOfInterestNb) of SMEs, as
demonstrated by the "letters of interest" that have been collected during the preparation
of the project and presented in annexe~\ref{lettre-soutien}.

\subsection{Indusrial Interest in COACH}

\subsubsection*{Partner: \textit{\mds}}

\mustbecompleted{Emanuel ....}

\subsubsection*{Partner: \textit{\bull}}
The team of \bull participating to the COACH project is from the Server Development
Department who is in charge of developing hardware for open servers (e.g. NovaScale) and
HPC solutions. The main expectation from COACH is to derive a new component (fine-grain
FPGA parallelism) to add to existing Bull HPC solutions.

%\subsubsection*{Partner: \textit{\xilinx}}
%Computing power potential of our FPGA architectures
%growing very quickly on one side, and complexity of designs implemented
%using our FPGAs dramatically increasing on the other side, it is very
%interesting for us to get high level design methodologies progressing
%quickly and targetting our FPGAs in the most possible efficient way.
%\parlf
%\xilinx goal is to get COACH to generate bitstream optimized as much as possible for
%\xilinx FPGAs in order to both, validate the methodology on our FPGA families, and ease
%future work of our customers.

\subsubsection*{Partner: \textit{\thales}}
\noindent
\thales has two main reasons to use the COACH platform:
\begin{itemize}
  \item The huge increase of the complexity of the systems in particular by their
  heterogeneity, raises the issues of design cost and time in the same proportion. The
  divisions need a design tool which supports the implementation of the applications from
  algorithm description to the executable code on platforms composed of several general
  purpose processors and dedicated IPs.
  \item The applications are more and more complex and adaptable to the environment which
  leads to a mixture of control aspects and data stream computing aspects. A new approach
  is necessary to be able to describe this type of application and manage the high level
  synthesis of system embedding control and data flow aspects.
\end{itemize}
\parlf
TRT (Thales Research and Technology) has the mission to assess and de-risk the emerging
technologies in its domains of expertise. Specifically in COACH, the studied technology is
a method and associated tools to make the bridge between application capture at system
level and the implementation on heterogeneous distributed computing architectures. The
main stake for Thales behind this is the future design process that will be applied to its
system teams in the future for the computation-intensive sensor applications. In a context
of very instable market of tools for parallel programming, it is important to experiment
and demonstrate the candidate technologies.
\\
In its role of internal dissemination, TRT will make the demonstration of the full design
flow within Thales, and will keep available a platform to later evaluate additional
applications coming from the Business Units.
\\
The COACH platform will be used in the new \thales products in which the algorithms are more
and more dependent of the environment and have to permanently adapt their behavior in
varying environments. The target markets are the critical infrastructures security and
border monitoring.

\subsubsection*{Industrial supports}

\mustbecompleted{NON A JOUR}
The following SMEs demonstrate interest to the COACH project (see the "letters of
interest" in annexe~\ref{lettre-soutien}) and will follow the COACH evolution and will
evaluate it:
\letterOfInterest{ALTERA Corporation}{lettres/Altera1.pdf},
\letterOfInterestPlus{lettres/Altera2.pdf}
\letterOfInterest{ADACSYS}{lettres/Coach_ADACSYS_lettre_interet},
\letterOfInterest{MAGILLEM Design Services}{lettres/Coach_lettre_interet_MDS},
\letterOfInterest{INPIXAL}{lettres/inpixal.jpg},
\letterOfInterest{CAMKA System}{lettres/CAMKA-System.pdf},
\letterOfInterest{ATEME}{lettres/ATEME.pdf},
\letterOfInterest{ALSIM Simulateur}{lettres/Alsim.pdf},
\letterOfInterest{SILICOMP-AQL}{lettres/itlabs.pdf},
\letterOfInterest{ABOUND Logic}{lettres/abound.pdf},
\letterOfInterest{EADS-ASTRIUM}{lettres/Astrium1.pdf}.
\letterOfInterestPlus{lettres/Astrium2.pdf}

\letterOfInterestClose

\subsection{Management of Intellectual Property}
A global consortium agreement will be defined during the first six monts of the project.
As already stated, the COACH project has been prepared during one year by a monthly meeting 
involving the five academic partners. The general free software policy described in the 
previous section has been agreed by academic partners  and has been
approved by all industrial participants. This free software policy will 
simplify the definition of the consortium agreement.