source: anr-2010/task-5.tex @ 385

Last change on this file since 385 was 237, checked in by coach, 15 years ago

Paul coquilles

File size: 6.4 KB
Line 
1% vim:set spell:
2% vim:spell spelllang=en:
3
4\begin{taskinfo}
5\let\BULL\leader
6\let\UPMC\enable
7\let\TIMA\enable
8\let\THALES\enable
9\let\XILINX\enable
10\end{taskinfo}
11%
12\begin{objectif}
13This task pools the features dedicated to HPC system design. It is described on
14figures~\ref{coach-flow} and \ref{archi-hpc}. It consists in
15\begin{itemize}
16\item Providing a software tool that helps the HPC designer to find a good partition of the initial application
17    (figure~\ref{archi-hpc}).
18\item specification of the communication schemes between the software part running on the PC and the
19FPGA-SoC.
20\item Implementing the communication scheme at all levels: partition help, software
21implementation both on the PC and in the operating system of the FPGA-SoC, hardware.
22\item Providing support for dynamic partial reconfiguration of \xilinx FPGA in order
23to optimize FPGA ressource usage.
24\end{itemize}
25
26The low level hardware transmission support will be the PCI/X bus which allows high bit-rate
27transfers. The reasons of this choice are that both \altera and \xilinx provide PCI/X IP for
28their FPGA and that GPU HPC softwares use also it.
29%This will allow us at least to be inspired by GPU communication schemes and may be to reuse
30%parts of the GPU softwares.
31
32\end{objectif}
33%
34\begin{workpackage}
35  \subtask
36    This \ST deals with the COACH HPC feature that consists in accelerating an existing
37    apllication running on a PC by migrating critical parts into a SoC implemented on an
38    FPGA plugged to the PC PCI/X bus.
39    The main steps and components of this \ST are:
40    \begin{itemize}
41      \item The definition of the communication middleware as a software API (Application
42        Programing Interface) between the application part running on the PC and the
43        application part running on the FPGA-SoC.
44      \item A software for helping the end-user to partition applications (figure~\ref{archi-hpc}).
45        This software is a library implementing the communication API with features to profile
46        the partitioned application.
47      \item The implementation of the communication API on the both sides (PC part and FPGA-SoC).
48    \end{itemize}
49    \begin{livrable}
50      \itemL{0}{6}{d}{\Sbull}{HPC communication API}{3:0:0}
51        \setMacroInAuxFile{hpcCommApi}
52        Specification describing the API.
53      \itemL{6}{12}{x}{\Supmc}{HPC partionning helper}{1:0:0}
54        \setMacroInAuxFile{hpcCommHelper}
55        A library implementing the communication API defined in the {\hpcCommApi} deliverable.
56        This library is dedicated to help the end-user to partition an applicattion for
57        HPC.
58      \itemL{12}{21}{x}{\Supmc}{HPC API for Linux PC}{0:2.5:0}
59        \setMacroInAuxFile{hpcCommLinux}
60        The PC part of the HPC communication API that comminicates with the FPGA-SOC, a
61        library and probably a LINUX module.
62      \itemL{12}{21}{x}{\Supmc}{HPC API for MUTEKH OS}{0:2.5:0}
63        \setMacroInAuxFile{hpcMutekDriver}
64        The FPGA-SoC part of the communication API, a driver.
65      \itemL{21}{24}{x}{\Stima}{HPC API for DNA OS}{0:3:0}
66        \setMacroInAuxFile{hpcDnaDriver}
67        Port of the {\hpcMutekDriver} driver on the DNA OS.
68      \itemL{24}{33}{x}{\Supmc}{HPC API}{0:0:1}
69        Bug corrections and enhancements of communication middleware
70        (\novers{\hpcCommApi}, \novers{\hpcCommHelper}, \novers{\hpcCommLinux},
71        \novers{\hpcMutekDriver}, \novers{\hpcDnaDriver}).
72    \end{livrable}
73
74\subtask This \ST deals with the implementation of hardware and SystemC modules
75    required by the neutral architectural template for using the PCI/X IP of \altera and \xilinx.
76    \begin{livrable}
77    \itemL{9}{18}{h}{\Stima}{HPC hardware \xilinx}{3:9:0}
78        \setMacroInAuxFile{hpcPlbBridge}
79        The synthesizable VHDL description of a PLB/VCI bridge and its corresponding SystemC model.
80    \itemL{9}{18}{h}{\Supmc}{HPC hardware \altera}{1:2:0}
81        \setMacroInAuxFile{hpcAvalonBridge}
82        The synthesizable VHDL description of an AVALON/VCI bridge and its corresponding SystemC model.
83    \itemL{9}{24}{h}{\Supmc}{PCI/X traffic generator}{1:1:0}
84        The SystemC description of a component that generates PCI/X traffic. It is
85        required to prototype FPGA-SoC dedicated to HPC.
86    \end{livrable}
87
88\subtask This \ST consists in integrating dynamic partial reconfiguration of \xilinx FPGA in the CSG design flow.
89It also includes appropriate SoC-FPGA OS drivers and a modification of the profiling library.
90    \begin{livrable}
91    \itemL{24}{36}{x}{\Supmc}{CSG support for \ganttlf reconfiguration}{0:0:2}
92        Modification of the CSG software to support statically reconfigurable tasks.
93    \itemL{18}{36}{x}{\Stima}{CSG module for \ganttlf dynamic reconfiguration}{0:4:12}
94                This livrable is a CSG module allowing to partition the task graph along
95                the dynamic partial reconfiguration regions. The resulting task-region assignement
96                is directly used for generation of bitstreams. The module also produces reconfiguration
97                management software to be run on the SoC-FPGA.
98    \itemL{18}{30}{x}{\Stima}{Dynamic reconfiguration \ganttlf for DNA drivers}{0:3:3}
99        \setMacroInAuxFile{hpcDynconfDriver}
100            The drivers required by the DNA OS in order to manage dynamic partial
101        reconfiguration inside the SoC-FPGA.
102    \itemL{30}{36}{x}{\Supmc}{Dynamic reconfiguration \ganttlf for  MUTEKH drivers}{0:0:1}
103        Port of the {\hpcDynconfDriver} drivers on the MUTEKH OS.
104    \itemL{24}{36}{x}{\Stima}{Profiler for \ganttlf dynamic reconfiguration}{0:0:6}
105        Extension of the HPC partionning helper in order to integrate dynamic partial
106        reconfiguration dedicated features (reconfiguration time of regions, variable
107        number of coprocessors).
108    \itemL{24}{36}{d}{\Sxilinx}{Optimisation for \xilinx \ganttlf dynamic reconfiguration}{0:0:2}
109        \xilinx will work with \tima in order to better take into account during
110        partitioning decisions specific constraints due to partial reconfiguration process.
111        The deliverable is a document describing the \xilinx specific constraints.
112    \end{livrable}
113%\item This \ST is the delivery of 2 PCI/X \mustbecompleted{FIXME: Stratix4} FPGA board
114%   with its PCI/X IP. These boards are dedicated to the COACH HPC development.
115%   They are based on \mustbecompleted{FIXME:stratix4} FPGA device of 400,000 LUT.
116%   \begin{livrable}
117%   \itemL{0}{6}{m}{\Saltera}{HPC development boards}{0:0:0} Two PCI/X FPGA boards.
118%   \end{livrable}
119\end{workpackage}
Note: See TracBrowser for help on using the repository browser.