Changeset 237 for anr/task-5.tex

Timestamp:

Feb 16, 2010, 5:24:12 PM (14 years ago)

Author:

coach

Message:

Paul coquilles

File:

• anr/task-5.tex (modified) (2 diffs)

anr/task-5.tex

@@ -25 +25 @@
 
 The low level hardware transmission support will be the PCI/X bus which allows high bit-rate
-transfers. The reasons of this choices are that both \altera and \xilinx provide PCI/X IP for
+transfers. The reasons of this choice are that both \altera and \xilinx provide PCI/X IP for
 their FPGA and that GPU HPC softwares use also it.
 %This will allow us at least to be inspired by GPU communication schemes and may be to reuse
@@ -90 +90 @@
     \begin{livrable}
     \itemL{24}{36}{x}{\Supmc}{CSG support for \ganttlf reconfiguration}{0:0:2}
-        Modification of CSG software to support statically reconfigurable task.
+        Modification of the CSG software to support statically reconfigurable tasks.
     \itemL{18}{36}{x}{\Stima}{CSG module for \ganttlf dynamic reconfiguration}{0:4:12}
-                This livrable is a CSG module allowing to partition the task graph on
+                This livrable is a CSG module allowing to partition the task graph along
                 the dynamic partial reconfiguration regions. The resulting task-region assignement
                 is directly used for generation of bitstreams. The module also produces reconfiguration