source: anr/anr.bib @ 316

Last change on this file since 316 was 313, checked in by coach, 14 years ago

Fixed references.
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1%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
2%%%%% MDS
3%Stuyt Jan, Wolfgang Ecker, Mayer Albrecht, Hustin Serge, Amerijckx Christophe,
4%de Paoli Serge and Vaumorin Emmanuel
5@inproceedings{mds1,
6  author    = {Kruijtzer Wido, Van der Wolf Pieter, de Kock Erwin and All},
7  title     = {Industrial IP integration flows based on IP-XACT standards},
8  booktitle = {Proceedings of the conference on Design, automation and test in Europe},
9  series    = {DATE'08},
10  year      = {2008},
11  isbn      = {978-3-9810801-3-1},
12  location  = {Munich, Germany},
13  pages     = {32--37},
14  numpages  = {6},
15  url       = {http://doi.acm.org/10.1145/1403375.1403386},
16  doi       = {http://doi.acm.org/10.1145/1403375.1403386},
17  acmid     = {1403386},
18  publisher = {ACM},
19  address   = {New York, NY, USA},
20} 
21
22@misc{mds2,
23  author       = {E. Vaumorin, M. Palus, F. Clermidy and J. Martin},
24  title        = {SPIRIT IP-XACT Controlled ESL Design Tool Applied to a Network-on-Chip Platform},
25  howpublished = {\url{http://www.design-reuse.com/articles/18613/ip-xact-esl-noc.html}},
26  year         = {2008},
27}
28
29@misc{socketflow,
30  author       = {L. Maillet-Contoz, R. Lucas and E. Vaumorin},
31  title        = {SocKET design flow and Application on industrial use cases},
32  howpublished = {\url{http://socket.imag.fr/Presentations-socket/Vendredi15/Presentation_flot.pdf}},
33  note         = {home site: \url{http://socket.imag.fr/}},
34  year         = {2010},
35}
36
37@techreport{rapport-ministere,
38 author      = {Eric Bant\'egnie, Claude Lepape, Jean-Luc Dormoy},
39 title       = {Briques g\'en\'eriques du logiciel embarqu\'e},
40 year        = {2010},
41 institution = {Mininist\'ere de l'industrie},
42}
43
44%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
45%%%%% LIP6
46% HPC
47@InProceedings{hpc06a,
48  author    = {{M.B. Gokhale and al.}},
49  title     = {{Promises and Pitfalls of Reconfigurable Supercomputing}},
50  booktitle = {Systems and Algorithms, CSREA Press},
51  pages     = {11-20},
52  year      = {2006},
53}
54@MISC{hpc06b,
55  author =       {{D. Buell}},
56  title  =   {{Programming Reconfigurable Computers}},
57  booktitle = {Summer Institute},
58  howpublished = {http://gladiator.ncsa.uiuc.edu/PDFs/rssi06/presentations/00\_Duncan\_Buell.pdf},
59  year =         {2006},
60}
61@InProceedings{hpc07a,
62  author =       {{T. Van Court and al.}},
63  title  =   {{ Achieving High Performance with FPGA-Based Computing}},
64  booktitle = {Computer, vol. 40, no. 3},
65  pages     = {50-57},
66  month     = {mars},
67  year =         {2007},
68}
69@misc{hpc08,
70  title        = {Mitrionics},
71  howpublished = {http://www.mitrionics.com/},
72  year         = {2009},
73}
74@misc{hpc09,
75  title        = {Gidel},
76  howpublished = {http://www.gidel.com/},
77  year         = {2009},
78}
79@misc{hpc10,
80  title        = {Convey Computer},
81  howpublished = {http://www.conveycomputers.com/},
82  year         = {2009},
83}
84@InProceedings{hpc11,
85  author =      {E. El-Araby, I. Gonzalez and T. El-Ghazawi},
86  title   = {Virtual Architecture and Design Automation for Partial Reconfiguration },
87  booktitle = {HPRCTA},
88  year =         {2008},
89}
90@InProceedings{hpc12,
91  author =       {{P. Lysaght and J. Dunlop}},
92  title   = {Dynamic Reconfiguration of Field Programmable Gate Arrays},
93  booktitle = {Field Programmable Logic and Applications, Oxford, England},
94  month     = {Sept},
95  year =         {1993},
96}
97
98
99% System design
100@misc{soclib,
101  title        = {Soclib},
102  howpublished = {http://www.soclib.fr/},
103  year         = {2009},
104}
105
106@misc{system-generateur-for-dsp,
107  title        = {{System Generator for DSP}},
108  howpublished = {http://www.xilinx.com/tools/sysgen.htm},
109  year         = {2009},
110}
111
112@misc{spoc-builder,
113  title        = {{sopc builder support}},
114  howpublished = {http://www.altera.com/support/software/system/sopc/sof-sopc\_builder.html},
115  year         = {2009},
116}
117
118@InProceedings{cosy,
119    author = { J.Y Brunel, al },
120    title  = { COSY: a methodology for system design based on reusable hardware \& software IP's},
121    booktitle = { Technologies for the Information Society },
122    publisher = { IOS Press },
123    year      = {1998},
124    pages     = {709-716},
125}
126
127@InProceedings{disydent05,
128  author =       {{Ivan Aug\'{e}, Fr\'{e}d\'{e}ric P\'{e}trot, Fran\c{c}ois Donnet and Pascal Gomez}},
129  title =        {{Platform-based design from parallel C specifications}},
130  booktitle = {IEEE Transaction on CAD of Integrated Circuits and Systems},
131  pages     = {1811--1826},
132  month     = {December},
133  year =         {2005},
134}
135@inproceedings{dspin08,
136 author = {Miro-Panades, Ivan and Clermidy, Fabien and Vivet, Pascal and Greiner, Alain},
137 title = {Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture},
138 booktitle = {NOCS '08: Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip},
139 year = {2008},
140 isbn = {978-0-7695-3098-7},
141 pages = {139--148},
142 publisher = {IEEE Computer Society},
143 address = {Washington, DC, USA},
144 }
145
146
147% HLS
148% http://mesl.ucsd.edu/spark/index.shtml
149@INBOOK{spark04,
150  author     = {S. Gupta and al.},
151  title      = {SPARK: A Parallelizing Approach to the High-Level Synthesis of Digital Circuits},
152  publisher  = {Springer},
153  year       = {2004},
154}
155
156
157@INBOOK{ugh08,
158  author    = {Ivan Aug\'{e} and Fr\'{e}d\'{e}ric P\'{e}trot},
159  title     = {User Guided High Level Synthesis},
160  booktitle = {High-Level Synthesis: From Algorithm to Digital Circuits},
161  publisher = {Springer},
162  year      = {2008},
163  chapter   = {10},
164  pages     = {139-148},
165}
166  %editor    = { Philippe Coussy and Adam Moriawiec},
167
168@misc{pico,
169  title        = {{PICO}},
170  howpublished = {http://www.synfora.com/},
171  year         = {2009},
172}
173
174@misc{catapult-c,
175  title        = {{CATAPULT-C Mentor HLS tool}},
176  howpublished = {http://www.mentor.com/products/esl/high\_level\_synthesis/},
177  year         = {2009},
178}
179
180@misc{cynthetizer,
181  title        = {{Forte's CYNTHESIZER}},
182  howpublished = {http://www.forteds.com/},
183  year         = {2009},
184}
185
186@inproceedings{IP-XACT-08,
187 author = {Kruijtzer, Wido and van der Wolf, Pieter and de Kock, Erwin and Stuyt, Jan and Ecker, Wolfgang and Mayer, Albrecht and Hustin, Serge and Amerijckx, Christophe and de Paoli, Serge and Vaumorin, Emmanuel},
188 title = {Industrial IP integration flows based on IP-XACT standards},
189 booktitle = {Proceedings of the conference on Design, automation and test in Europe},
190 series = {DATE '08},
191 year = {2008},
192 isbn = {978-3-9810801-3-1},
193 location = {Munich, Germany},
194 pages = {32--37},
195 numpages = {6},
196 url = {http://doi.acm.org/10.1145/1403375.1403386},
197 doi = {http://doi.acm.org/10.1145/1403375.1403386},
198 acmid = {1403386},
199 publisher = {ACM},
200 address = {New York, NY, USA},
201}
202
203
204%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
205%%% UBS
206
207@INBOOK{IEEEDT,
208author = {Philippe Coussy and Andres Takach},
209title = {Special Issue on High-Level Synthesis},
210journal ={IEEE Design and Test of Computers},
211volume = {25},issn = {0740-7475},
212year = {2008},
213pages = {393},doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2008.147},
214publisher = {IEEE Computer Society},
215address = {Los Alamitos, CA, USA},}
216
217
218@BOOK{HLSBOOK,
219  author    = {P. Coussy and A. Morawiec},
220  title = {High-Level Synthesis: From Algorithm to Digital Circuits},
221  publisher = {Springer},
222  year      = {2008},
223}
224
225@BOOK{CATRENE,
226  author    = {CATRENE, Cluster for Application and Technology Research in Europe on NanotElectronics},
227  title = {European Roadmap for EDA},
228  publisher = {CATRENE, Cluster for Application and Technology Research in Europe on NanotElectronics},
229  year      = {2009},
230}
231
232@INBOOK{gaut08,
233  author    = {P. Coussy and al.},
234  title     = {GAUT: A High-Level Synthesis Tool for DSP applications},
235  booktitle = {High-Level Synthesis: From Algorithm to Digital Circuits},
236  publisher = {Springer},
237  year      = {2008},
238}
239
240@article{DBLP:journals/dt/CoussyT09,
241  author    = {Philippe Coussy and
242               Andres Takach},
243  title     = {Guest Editors' Introduction: Raising the Abstraction Level
244               of Hardware Design},
245  journal   = {IEEE Design {\&} Test of Computers},
246  volume    = {26},
247  number    = {4},
248  year      = {2009},
249  pages     = {4-6},
250  ee        = {http://doi.ieeecomputersociety.org/10.1109/MDT.2009.80},
251  bibsource = {DBLP, http://dblp.uni-trier.de}
252}
253
254
255@article{DBLP:journals/dt/CoussyGMT09,
256  author    = {Philippe Coussy and
257               Daniel D. Gajski and
258               Michael Meredith and
259               Andres Takach},
260  title     = {An Introduction to High-Level Synthesis},
261  journal   = {IEEE Design {\&} Test of Computers},
262  volume    = {26},
263  number    = {4},
264  year      = {2009},
265  pages     = {8-17},
266  ee        = {http://doi.ieeecomputersociety.org/10.1109/MDT.2009.69},
267  bibsource = {DBLP, http://dblp.uni-trier.de}
268}
269
270
271@article{DBLP:journals/vlsisp/ThabetCHM09,
272  author    = {Farhat Thabet and
273               Philippe Coussy and
274               Dominique Heller and
275               Eric Martin},
276  title     = {Exploration and Rapid Prototyping of DSP Applications using
277               SystemC Behavioral Simulation and High-level Synthesis},
278  journal   = {Signal Processing Systems},
279  volume    = {56},
280  number    = {2-3},
281  year      = {2009},
282  pages     = {167-186},
283  ee        = {http://dx.doi.org/10.1007/s11265-008-0235-1},
284  bibsource = {DBLP, http://dblp.uni-trier.de}
285}
286
287
288
289@inproceedings{CHAVET:2007:HAL-00153994:1,
290        title = { {A} {M}ethodology for {E}fficient {S}pace-{T}ime {A}dapter {D}esign {S}pace {E}xploration: {A} {C}ase {S}tudy of an {U}ltra {W}ide {B}and {I}nterleaver},
291        author = {{C}havet, {C}yrille and {C}oussy, {P}hilippe and {U}rard, {P}ascal and {M}artin, {E}ric},
292        abstract = {{T}his paper presents a solution to efficiently explore the design space of communication adapters. {I}n most digital signal processing ({DSP}) applications, the overall architecture of the system is significantly affected by communication architecture, so the designers need specifically optimized adapters. {B}y explicitly modeling these communications within an effective graph-theoretic model and analysis framework, we automatically generate an optimized architecture, named {S}pace-{T}ime {A}dapte{R} ({STAR}). {O}ur design flow inputs a {C} description of {I}nput/{O}utput data scheduling, and user requirements (throughput, latency, parallelism...), and formalizes communication constraints through a {R}esource {C}onstraints {G}raph ({RCG}). {T}he {RCG} properties enable an efficient architecture space exploration in order to synthesize a {STAR} component. {T}he proposed approach has been tested to design an industrial data mixing block example: an {U}ltra-{W}ideband interleaver.},
293        language = {{A}nglais},
294        affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud - {STM}icroelectronics - {STM} - {STM}icroelectronics },
295        booktitle = {{P}roceedings of the {IEEE} {I}nternational {S}ymposium on {C}ircuits and {S}ystems ({ISCAS}) {T}he {IEEE} {I}nternational {S}ymposium on {C}ircuits and {S}ystems ({ISCAS}) },
296        publisher = {{L}ibrary of {C}ongress },
297        pages = {2946 },
298        address = {{N}ew {O}rleans {\'E}tats-{U}nis d'{A}m{\'e}rique },
299        editor = {{IEEE} },
300        note = {{ISBN}:1-4244-0921-7 },
301        audience = {internationale },
302    day = {28},
303    month = {05},
304    year = {2007},
305    URL = {http://hal.archives-ouvertes.fr/hal-00153994/en/},
306    URL = {http://hal.archives-ouvertes.fr/hal-00153994/PDF/ISCAS_Chavet1992.pdf},
307}
308
309
310@inproceedings{DBLP:conf/iccad/ChavetACCJUM07,
311  author    = {Cyrille Chavet and
312               Caaliph Andriamisaina and
313               Philippe Coussy and
314               Emmanuel Casseau and
315               Emmanuel Juin and
316               Pascal Urard and
317               Eric Martin},
318  title     = {A design flow dedicated to multi-mode architectures for
319               DSP applications},
320  booktitle = {ICCAD},
321  year      = {2007},
322  pages     = {604-611},
323  ee        = {http://doi.acm.org/10.1145/1326073.1326199},
324  crossref  = {DBLP:conf/iccad/2007},
325  bibsource = {DBLP, http://dblp.uni-trier.de}
326}
327
328
329@inproceedings{DBLP:conf/glvlsi/ChavetCUM07,
330  author    = {Cyrille Chavet and
331               Philippe Coussy and
332               Pascal Urard and
333               Eric Martin},
334  title     = {A design methodology for space-time adapter},
335  booktitle = {ACM Great Lakes Symposium on VLSI},
336  year      = {2007},
337  pages     = {347-352},
338  ee        = {http://doi.acm.org/10.1145/1228784.1228868},
339  crossref  = {DBLP:conf/glvlsi/2007},
340  bibsource = {DBLP, http://dblp.uni-trier.de}
341}
342
343
344@inproceedings{CHAVET:2007:HAL-00154025:1,
345        title = { {A}pplication of a design space exploration tool to enhance interleaver generation},
346        author = {{C}havet, {C}yrille and {C}oussy, {P}hilippe and {U}rard, {P}ascal and {M}artin, {E}ric},
347        abstract = {{T}his paper presents a methodology to efficiently explore the design space of communication adapters. {I}n most digital signal processing ({DSP}) applications, the overall performance of the system is significantly affected by communication architectures, as a consequence the designers need specifically optimized adapters. {B}y explicitly modeling these communications within an effective graph-theoretic model and analysis framework, we automatically generate an optimized architecture, named {S}pace-{T}ime {A}dapte{R} ({STAR}). {O}ur design flow inputs a {C} description of {I}nput/{O}utput data scheduling, and user requirements (throughput, latency, parallelism...), and formalizes communication constraints through a {R}esource {C}onstraints {G}raph ({RCG}). {D}esign space exploration is then performed through associated tools, to synthesize a {STAR} component under time-to-market constraints. {T}he proposed approach has been tested to design an industrial data mixing block example: an {U}ltra-{W}ideband interleaver.},
348        language = {{A}nglais},
349        affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud - {STM}icroelectronics - {STM} - {STM}icroelectronics },
350        booktitle = {{P}roceedings of the {E}uropean {S}ignal {P}rocessing {C}onference ({EUSIPCO}-2007) {E}uropean {S}ignal {P}rocessing {C}onference ({EUSIPCO}-2007) },
351        publisher = {{E}urasip },
352        pages = {??? },
353        address = {{P}oznan {P}ologne },
354        audience = {internationale },
355    day = {03},
356    month = {09},
357    year = {2007},
358    URL = {http://hal.archives-ouvertes.fr/hal-00154025/en/},
359    URL = {http://hal.archives-ouvertes.fr/hal-00154025/PDF/EUSIPCO_chavet.pdf},
360}
361
362
363@inproceedings{ANDRIAMISAINA:2007:HAL-00153086:1,
364        title = { {S}ynthesis of {M}ultimode digital signal processing systems},
365        author = {{A}ndriamisaina, {C}aaliph and {C}asseau, {E}mmanuel and {C}oussy, {P}hilippe},
366        abstract = {{I}n this paper, we propose a design methodology for implementing a multimode (or multi-configuration) and multi-throughput system into a single hardware architecture. {T}he inputs of the design flow are the data flow graphs ({DFG}s), representing the different modes (i.e. the different applications to be implemented), with their respective throughput constraints. {W}hile traditional approaches merge {DFG}s together before the synthesis process, we propose to use ad-hoc scheduling and binding steps during the synthesis of each {DFG}. {T}he scheduling, which assigns operations to specific time steps, maximizes the similarity between the control steps and thus decreases the controller complexity. {T}he binding process, which assigns operations to specific functional units and data to specific storage elements, maximizes the similarity between datapaths and thus minimizes steering logic and register overhead. {F}irst results show the interest of the proposed synthesis flow.},
367        language = {{A}nglais},
368        affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud - {R}2{D}2 - {INRIA} - {IRISA} - {CNRS} : {UMR}6074 - {INRIA} - {I}nstitut {N}ational des {S}ciences {A}ppliqu{\'e}es de {R}ennes - {E}cole {N}ationale {S}up{\'e}rieure des {S}ciences {A}ppliqu{\'e}es et de {T}echnologie - {U}niversit{\'e} de {R}ennes 1 },
369        booktitle = {{P}roceeding of {A}daptive {H}ardware and {S}ystems {NASA}/{ESA} {C}onference on {A}daptive {H}ardware and {S}ystems },
370        publisher = {{AHS} },
371        pages = {7 },
372        address = {{E}dinburgh {R}oyaume-{U}ni },
373        audience = {internationale },
374    year = {2007},
375    URL = {http://hal.archives-ouvertes.fr/hal-00153086/en/},
376    URL = {http://hal.archives-ouvertes.fr/hal-00153086/PDF/PID411805.pdf},
377}
378
379
380@inproceedings{COUSSY:2005:HAL-00077301:1,
381        title = { {A} {M}ore {E}fficient and {F}lexible {DSP} {D}esign {F}low from {MATLAB}-{SIMULINK}},
382        author = {{C}oussy, {P}hilippe and {C}orre, {G}wenol{\'e} and {B}omel, {P}ierre and {S}enn, {E}ric and {M}artin, {E}ric},
383        abstract = {{T}he design of complex {D}igital {S}ignal {P}rocessing systems implies to minimize architectural cost and to maximize timing performances while taking into account communication and memory accesses constraints for the integration of dedicated hardware accelerator. {U}nfortunately, the traditional {M}atlab/{S}imulink design flows gather not very flexible hardware blocs. {I}n this paper, we present a methodology and a tool that permit the {H}igh-{L}evel {S}ynthesis of {DSP} applications, under both {I}/{O} timing and memory constraints. {B}ased on formal models and a generic architecture, this tool helps the designer in finding a reasonable trade-off between the circuit's latency and its architectural complexity. {T}he efficiency of our approach is demonstrated on the case study of a {FFT} algorithm.},
384        keywords = {{DSP} application, synthesis under memory and communication constraints},
385        language = {{A}nglais},
386        affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud },
387        booktitle = {{IEEE} {I}nternational {C}onference on {A}coustic, {S}peech and {S}ignal {P}rocessing },
388        publisher = {{IEEE} },
389        pages = {{V}ol. {V} p. 61-64 },
390        editor = {{IEEEE} },
391    year = {2005},
392    URL = {http://hal.archives-ouvertes.fr/hal-00077301/en/},
393    URL = {http://hal.archives-ouvertes.fr/hal-00077301/PDF/coussy_final.pdf},
394}
395
396
397
398%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
399%%%%% IRISA
400@InProceedings{KluterCodes08,
401  author =       {{Theo Kluter and  Philip Brisk and  Paolo Ienne and  and Edoardo Charbon}},
402  title =        {{Speculative DMA for Architecturally Visible Storage in Instruction Set Extensions}},
403  booktitle = {ISSS/CODES},
404  year =         {2008},
405}
406
407@InProceedings{KluterDAC09,
408  author =       {{Theo Kluter and  Philip Brisk and  Paolo Ienne and  and Edoardo Charbon}},
409  title =        {{Way Stealing : Cache-assisted Automatic Instruction Set Extensions}},
410  booktitle = {Design Automation Conference (DAC)},
411  year =         {2009},
412}
413
414@InProceedings{YuCodes04,
415  author =       {{Pan Yu and Tulika Mitra}},
416  title =        {{Scalable Custom Instructions Identification for Instruction Set Extensible Processors}},
417  booktitle = {ISSS/CODES},
418  year =         {2004},
419}
420
421@InProceedings{Dinh08,
422  author =       {{Quang Dinh and Deming Chen and Martin D.~F.~Wong}},
423  title =        {{Efficient ASIP Design for Configurable Processors with Fine-Grained Resource Sharing}},
424  booktitle = {ACM Internatibnal Conference Field Programmable Gate Arrays (FPGA)},
425  year =         {2008},
426}
427
428@Misc{NIOS2UG,
429  title =        {{Nios II Custom Instruction User Guide, Altera Corp.}},
430  year =         {2008},
431}
432
433%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
434%%% CITI
435@book{Polis,
436  author = {Balarin, Felice},
437  publisher = {Kluwer Academic Publishers},
438  title = {Hardware-software co-design of embedded systems : the POLIS
439        approach},
440  year = {1997}
441}
442
443@INPROCEEDINGS{Coware,
444  author = {Ivo Bolsens and Hugo J. De Man and Bill Lin and Karl Van
445                Rompaey and Steven Vercauteren and Diederik Verkest},
446  title = {Hardware/Software Co-Design of Digital Telecommunication Systems},
447  booktitle = {Proceedings of the IEEE},
448  year = {1997},
449  pages = {391--418}
450}
451
452@article{Jantsch,
453  author = {Mattias O'Nil and Axel Jantsch},
454  title = {Device Driver and DMA Controller Synthesis from HW/SW
455                        Communication protocol specifications},
456  journal = {Design Automation for Embedded Systems},
457  year = {2001},
458  volume = {6},
459  pages = {177-205}
460}
461
462@InProceedings{Park01,
463  author =   {Joonseok Park and Pedro C.~Diniz},
464  title =    {Synthesis of Pipelined Memory Access Controllers for Streamed
465                Data Applications on {FPGA}-Based Computing Engines},
466  booktitle =    {International Symposium on System Synthesis (ISSS)},
467  pages = {221-226},
468  year =     {2001},
469}
470
471@article{FR-vlsi,
472  author = {Antoine Fraboulet and Tanguy Risset},
473  title = {Master Interface for On-Chip Hardware Accelerator Burst Communications},
474  journal = {Journal of VLSI Signal Processing},
475  publisher = {Springer Science},
476  year = {2007},
477  volume = {59},
478  pages = {73-85}
479}
480
481@InProceedings{jerraya,
482  author =   {Sungjoo Yoo and Jerraya Ahmed},
483  title =    {Introduction to Hardware Abstraction Layers for SoC},
484  OPTcrossref =  {},
485  OPTkey =   {},
486  booktitle = {Design, Automation and Test in Europe Conference and Exhibition},
487  pages =    {336 -- 337},
488  year =     2003,
489  OPTeditor =    {},
490  OPTvolume =    {},
491  OPTnumber =    {},
492  OPTseries =    {},
493  OPTaddress =   {},
494  OPTmonth =     {},
495  OPTorganization = {},
496  OPTpublisher = {},
497  OPTnote =      {},
498  OPTannote =    {}
499}
500
501@INPROCEEDINGS{FAUST,
502  author = {D. Lattard and  E. Beigne and  C. Bernard and  C. Bour and  F.
503        Clermidy and  Y. Durand and  J. Durupt and  D. Varreau and  P. Vivet and
504        P. Penard and  A. Bouttier and  F. Berens}, 
505  title = "A Telecom Baseband Circuit-Based on an Asynchronous Network-on-Chip", 
506  pages = {},
507  BOOKTITLE="ISSCC\'2007", 
508  year = {2007},
509  publisher = {IEEE Computer Society},
510  address = {San Francisco, USA},
511};
512
513@inproceedings{JerrayaPetrot,
514 author = {Ahmed A. Jerraya and Aimen Bouchhima and Fr\'{e}d\'{e}ric P\'{e}trot},
515 title = {Programming models and HW-SW interfaces abstraction for multi-processor SoC},
516 booktitle = {DAC '06: Proceedings of the 43rd annual conference on Design automation},
517 year = {2006},
518 isbn = {1-59593-381-6},
519 pages = {280--285},
520 location = {San Francisco, CA, USA},
521 publisher = {ACM},
522 address = {New York, NY, USA},
523}
524
525@inproceedings{mwmr,
526 author = {E. Faure and A. Greiner and D. Genius},
527 title = {A generic hardware/software communication mechanism for
528          Multi-Processor System on Chip, Targeting Telecommunication Applications},
529 booktitle = {ReCoSoC'06},
530 year = {2006},
531 pages = {237--242},
532 address = {Montpellier, France}
533 }
534
535@inproceedings{Alberto,
536  author    = {Roberto Passerone and
537               James A. Rowson and
538               Alberto L. Sangiovanni-Vincentelli},
539  title     = {Automatic Synthesis of Interfaces Between Incompatible Protocols},
540  booktitle = {DAC},
541  year      = {1998},
542  pages     = {8-13}
543}
544
545@article{Avnit,
546  author    = {Karin Avnit and
547               Vijay D'Silva and
548               Arcot Sowmya and
549               S. Ramesh and
550               Sri Parameswaran},
551  title     = {Provably correct on-chip communication: A formal approach
552               to automatic protocol converter synthesis},
553  journal   = {ACM Trans. Design Autom. Electr. Syst.},
554  volume    = {14},
555  number    = {2},
556  year      = {2009}
557}
558
559@inproceedings{smith,
560  author    = {James Smith and
561               Giovanni De Micheli},
562  title     = {Automated Composition of Hardware Components},
563  booktitle = {DAC},
564  year      = {1998},
565  pages     = {14-19}
566}
567
568@inproceedings{Narayan,
569  author    = {Sanjiv Narayan and
570               Daniel Gajski},
571  title     = {Interfacing Incompatible Protocols Using Interface Process
572               Generation},
573  booktitle = {DAC},
574  year      = {1995},
575  pages     = {468-473}
576}
577
578@TECHREPORT{Ptolemy,
579  AUTHOR       = { E.A. Lee et al.},
580  INSTITUTION  = {University of California, Berkeley},
581  NUMBER       = {UCB/ERL No. M99/37},
582  TITLE        = {Overview of the Ptolemy Project},
583  YEAR         = {1999},
584  MONTH        = {july}
585}
586
587@article{syntol,
588    author={Paul Feautrier},
589    title={Scalable and Structured Scheduling},
590    journal={Int. J. of Parallel Programming},
591    year=2006,
592    month=May, number=5, volume=34,
593    pages="459--487"
594}
595
596@InProceedings{bee,
597  author={Christophe Alias and Fabrice Baray and Alain Darte},
598  title={Bee+Cl@k: An Implementation of Lattice-Based Array Contraction in the Source-to-Source Translator ROSE},
599  booktitle = {LCTES},
600  year = {2007},
601  publisher = {ACM}
602}
603
604%%%%%%%%%%%%% ASIP %%%%%%%%%%%%%%%%
605
606@inproceedings{DAC09,
607 author = {Kluter, Theo and Brisk, Philip and Ienne, Paolo and Charbon, Edoardo},
608 title = {Way Stealing: cache-assisted automatic instruction set extensions},
609 booktitle = {DAC '09: Proceedings of the 46th Annual Design Automation Conference},
610 year = {2009},
611 isbn = {978-1-60558-497-3},
612 pages = {31--36},
613 location = {San Francisco, California},
614 doi = {http://doi.acm.org/10.1145/1629911.1629923},
615 publisher = {ACM},
616 address = {New York, NY, USA},
617 }
618
619@inproceedings{CODES08,
620 author = {Kluter, Theo and Brisk, Philip and Ienne, Paolo and Charbon, Edoardo},
621 title = {Speculative DMA for architecturally visible storage in instruction set extensions},
622 booktitle = {CODES/ISSS '08: Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis},
623 year = {2008},
624 isbn = {978-1-60558-470-6},
625 pages = {243--248},
626 location = {Atlanta, GA, USA},
627 doi = {http://doi.acm.org/10.1145/1450135.1450191},
628 publisher = {ACM},
629 address = {New York, NY, USA},
630 }
631 
632@article{TVLSI06,
633        author = {Cong, Jason and Han, Guoling and Zhang, Zhiru},
634 title = {Architecture and compiler optimizations for data bandwidth improvement in configurable processors},
635 journal = {IEEE Trans. Very Large Scale Integr. Syst.},
636 volume = {14},
637 number = {9},
638 year = {2006},
639 issn = {1063-8210},
640 pages = {986--997},
641 doi = {http://dx.doi.org/10.1109/TVLSI.2006.884050},
642 publisher = {IEEE Educational Activities Department},
643 address = {Piscataway, NJ, USA},
644}
645
646
647@Book{NIOS2,
648  title =        {{Nios II Processor Reference Handbook}},
649  publisher =    {Altera},
650  year =         {2009},
651}
652
653
654@inproceedings{ARC08,
655 author = {Galuzzi, Carlo and Bertels, Koen},
656 title = {The Instruction-Set Extension Problem: A Survey},
657 booktitle = {ARC '08: Proceedings of the 4th international workshop on Reconfigurable Computing},
658 year = {2008},
659 isbn = {978-3-540-78609-2},
660 pages = {209--220},
661 location = {London, UK},
662 doi = {http://dx.doi.org/10.1007/978-3-540-78610-8_21},
663 publisher = {Springer-Verlag},
664 address = {Berlin, Heidelberg},
665 }
666
667@inproceedings{CODES99,
668 author = {Charot, Fran\c{c}ois and Mess\'{e}, Vincent},
669 title = {{A flexible code generation framework for the design of application specific programmable processors}},
670 booktitle = {CODES '99: Proceedings of the seventh international workshop on Hardware/software codesign},
671 year = {1999},
672 pages = {27--31},
673 location = {Rome, Italy},
674 publisher = {ACM},
675 address = {New York, NY, USA},
676 }
677
678@inproceedings{ASAP05,
679 author = {L'Hours, Ludovic},
680 title = {{Generating Efficient Custom FPGA Soft-Cores for Control-Dominated Applications}},
681 booktitle = {ASAP '05: Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors},
682 year = {2005},
683 pages = {127--133},
684 publisher = {IEEE Computer Society},
685 address = {Washington, DC, USA},
686}
687
688@inproceedings{roma,
689 author = {Menard, Daniel and Casseau, Emmanuel and Khan, Shafqat and Sentieys, Olivier and Chevobbe, St\'{e}phane and Guyetant, St\'{e}phane and David, Raphael},
690 title = {Reconfigurable Operator Based Multimedia Embedded Processor},
691 booktitle = {ARC '09: Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications},
692 year = {2009},
693 pages = {39--49},
694 location = {Karlsruhe, Germany},
695 publisher = {Springer-Verlag},
696 address = {Berlin, Heidelberg},
697 }
698
699%%%%%%%%%%%%% AUTRES %%%%%%%%%%%%%%%%
700
701@inproceedings{thales-viola,
702 author = {Viola, Jones},
703 title = {{Rapid Object Detection using a Boosted Cascade of Simple Feature}},
704 booktitle = {Proceedings of Conference on Computer Vision and Pattern recognition},
705 year = {2001},
706}
707@INPROCEEDINGS{FP:96
708        ,AUTHOR = "Paul Feautrier"
709        ,TITLE = "Automatic Parallelization in the Polytope Model"
710        ,BOOKTITLE = "The Data-Parallel Programming Model"
711        ,YEAR = 1996   
712        ,EDITOR = "Guy-Ren\'e Perrin and Alain Darte"
713        ,PAGES = "79--103"
714        ,VOLUME = "LNCS 1132"
715        ,PUBLISHER = "Springer"
716}
717
718@book{DRV:2000,
719    author={Alain Darte and Yves Robert and Fr\'ed\'eric Vivien},
720    title={Scheduling and automatic Parallelization},
721    publisher={Birkh\"auser}, year=2000
722}
723
724@Article{Feau:92aa,
725  author =       "Paul Feautrier",
726  title =        "Some Efficient Solutions to the Affine Scheduling
727                 Problem, {I}, One Dimensional Time",
728  volume =       "21",
729  number =       "5",
730  month =        Oct,
731  pages =        "313--348",
732  journal =      "Int. J. of Parallel Programming",
733  year =         "1992"
734}
735
736@Article{Feau:92bb,
737  author =       "Paul Feautrier",
738  title =        "Some Efficient Solutions to the Affine Scheduling
739                 Problem, {II}, Multidimensional Time",
740  volume =       "21",
741  number =       "6",
742  journal =      "Int. J. of Parallel Programming",
743  month =        Dec,
744  pages =        "389--420",
745  year =         "1992"
746}
747
748@ARTICLE{Feau:96
749        ,AUTHOR = {Paul Feautrier}
750        ,TITLE = {Distribution Automatique des Donn\'es et des
751         calculs} 
752        ,JOURNAL = {T.S.I.}
753        ,YEAR = 1996, VOLUME = 15, NUMBER = 5, PAGES = {529--557}
754}
755
756%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
757%%% IA
758
759@PHDTHESIS{ia-hdr-phd,
760  author    = {Ivan Aug\'{e}},
761  title     = {Th\`ese d'Habilitation \`a Diriger des Recherches:
762               Synth\`ese de haut niveau \& Int\'egration
763               des syst\`emes mat\'eriel/logiciel},
764  school    = {Universit\'e Pierre et Marie Curie},
765  year      = {2009},
766  month     = {12},
767}
768
769@MISC{ia-hdr,
770  author    = {Ivan Aug\'{e}},
771  title     = {Th\`ese d'Habilitation \`a Diriger des Recherches:
772               Synth\`ese de haut niveau \& Int\'egration
773               des syst\`emes mat\'eriel/logiciel},
774  howpublished = {Universit\'e Pierre et Marie Curie},
775  year      = {2009},
776  month     = {12},
777}
778
779@INBOOK{ia-ugh08,
780  author    = {Ivan Aug\'{e} and Fr\'{e}d\'{e}ric P\'{e}trot},
781  title     = {User Guided High Level Synthesis},
782  booktitle = {High-Level Synthesis: From Algorithm to Digital Circuits},
783  publisher = {Springer},
784  chapter   = {10},
785  year      = {2008},
786  pages     = {139-148},
787}
788  %editor    = {Philippe Coussy and Adam Moriawiec},
789
790@misc{ia-ugh-09-aspdac,
791  author   = {Fr\'ed\'eric P\'etrot and Ivan Aug\'e},
792  title    = {User Guided High Level Synthesis},
793  booktitle= {Workshop "High-Level Synthesis: Next Step to Efficient ESL Design",
794                      in conjunction with ASP-DAC},
795  year     = {2009},
796}
797
798@misc{ia-ugh-08-date,
799  author =  {Fr\'ed\'eric P\'etrot and Ivan Aug\'e},
800  title = {User Guided High Level Synthesis},
801  booktitle= { Workshop "The New Wave of the High-Level Synthesis",
802                      in conjunction with DATE},
803  year       = {2008},
804}
805
806%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
807%%% AG
808
809@article{ag-1,
810    author = {Zhen Zhang and Alain Greiner and Mounir Benabdenbi},
811    title = {Fully distributed initialization procedure for a 2D-Mesh NoC, including off-line BIST and partial deactivation of faulty components},
812    journal ={On-Line Testing Symposium, IEEE International},
813    volume = {0},
814    isbn = {978-1-4244-7724-1},
815    year = {2010},
816    pages = {194-196},
817    doi = {http://doi.ieeecomputersociety.org/10.1109/IOLTS.2010.5560209},
818    publisher = {IEEE Computer Society},
819    address = {Los Alamitos, CA, USA},
820}
821
822@inproceedings{ag-2,
823    author    = {Greiner Alain and Faure Etienne and Pouillon Nicolas and Genius Dani\'ela},
824    title     = {A Generic Hardware/Software Communication Middleware for
825                 Streaming Applications on Shared Memory Multi Processor Systems-on-Chip},
826    booktitle = {Forum on Specification \& Design Languages (FDL 2009)},
827    isbn      = { 978-2-9530504-1-7},
828    month     = {September},
829    year      = {2009},
830    address   = {Nice, France},
831}
832
833@inproceedings{ag-3,
834    author    = {Porquet, Jo\"{e}l and Schwarz, Christian and Greiner, Alain},
835    title     = {Multi-compartment: A new architecture for secure
836                 co-hosting on SoC },
837    booktitle = {Proceedings of the 11th international conference on System-on-chip},
838    series    = {SOC'09},
839    month     = {October},
840    year      = {2009},
841    isbn      = {978-1-4244-4466-3},
842    location  = {Tampere, Finland},
843    pages     = {124-127},
844    numpages  = {4},
845    url       = {http://portal.acm.org/citation.cfm?id=1736530.1736555},
846    publisher = {IEEE Press},
847    address   = {Piscataway, NJ, USA},
848}
849
850@inproceedings{ag-4,
851    author    = {Miro-Panades, Ivan and Clermidy, Fabien and Vivet, Pascal and Greiner, Alain},
852    title     = {Physical Implementation of the DSPIN Network-on-Chip in the
853                 FAUST Architecture},
854    booktitle = {Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip},
855    series    = {NOCS'08},
856    year      = {2008},
857    month     = {April},
858    isbn      = {978-0-7695-3098-7},
859    location  = {Newcastle, UK},
860    pages     = {139-148},
861    numpages = {10},
862    url = {http://portal.acm.org/citation.cfm?id=1397757.1397994},
863    publisher = {IEEE Computer Society},
864    address   = {Washington, DC, USA},
865}
866
867
868
869%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
870%%% XXXX
871
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