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1	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
2	%%%%% MDS
3	@inproceedings{mds:2008,
4	author = {Kruijtzer Wido, Van der Wolf Pieter, de Kock Erwin, Stuyt Jan, Wolfgang Ecker, Mayer Albrecht, Hustin Serge, Amerijckx Christophe, de Paoli Serge and Vaumorin Emmanuel},
5	title = {Industrial IP integration flows based on IP-XACT standards},
6	booktitle = {Proceedings of the conference on Design, automation and test in Europe},
7	series = {DATE '08},
8	year = {2008},
9	isbn = {978-3-9810801-3-1},
10	location = {Munich, Germany},
11	pages = {32--37},
12	numpages = {6},
13	url = {http://doi.acm.org/10.1145/1403375.1403386},
14	doi = {http://doi.acm.org/10.1145/1403375.1403386},
15	acmid = {1403386},
16	publisher = {ACM},
17	address = {New York, NY, USA},
18	}
19
20	@report{rapportministere,
21	author = {Eric Bant\'egnie, Claude Lepape, Jean-Luc Dormoy},
22	title = {Briques g\'en\'eriques du logiciel embarqu\'e},
23	year = {2010},
24	publisher = {Mininist\'ere de l'industrie},
25	}
26
27	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
28	%%%%% LIP6
29	% HPC
30	@InProceedings{hpc06a,
31	author = {{M.B. Gokhale and al.}},
32	title = {{Promises and Pitfalls of Reconfigurable Supercomputing}},
33	booktitle = {Systems and Algorithms, CSREA Press},
34	pages = {11-20},
35	year = {2006},
36	}
37	@MISC{hpc06b,
38	author = {{D. Buell}},
39	title = {{Programming Reconfigurable Computers}},
40	booktitle = {Summer Institute},
41	howpublished = {http://gladiator.ncsa.uiuc.edu/PDFs/rssi06/presentations/00\_Duncan\_Buell.pdf},
42	year = {2006},
43	}
44	@InProceedings{hpc07a,
45	author = {{T. Van Court and al.}},
46	title = {{ Achieving High Performance with FPGA-Based Computing}},
47	booktitle = {Computer, vol. 40, no. 3},
48	pages = {50-57},
49	month = {mars},
50	year = {2007},
51	}
52	@misc{hpc08,
53	title = {Mitrionics},
54	howpublished = {http://www.mitrionics.com/},
55	year = {2009},
56	}
57	@misc{hpc09,
58	title = {Gidel},
59	howpublished = {http://www.gidel.com/},
60	year = {2009},
61	}
62	@misc{hpc10,
63	title = {Convey Computer},
64	howpublished = {http://www.conveycomputers.com/},
65	year = {2009},
66	}
67	@InProceedings{hpc11,
68	author = {E. El-Araby, I. Gonzalez and T. El-Ghazawi},
69	title = {Virtual Architecture and Design Automation for Partial Reconfiguration },
70	booktitle = {HPRCTA},
71	year = {2008},
72	}
73	@InProceedings{hpc12,
74	author = {{P. Lysaght and J. Dunlop}},
75	title = {Dynamic Reconfiguration of Field Programmable Gate Arrays},
76	booktitle = {Field Programmable Logic and Applications, Oxford, England},
77	month = {Sept},
78	year = {1993},
79	}
80
81
82	% System design
83	@misc{soclib,
84	title = {Soclib},
85	howpublished = {http://www.soclib.fr/},
86	year = {2009},
87	}
88
89	@misc{system-generateur-for-dsp,
90	title = {{System Generator for DSP}},
91	howpublished = {http://www.xilinx.com/tools/sysgen.htm},
92	year = {2009},
93	}
94
95	@misc{spoc-builder,
96	title = {{sopc builder support}},
97	howpublished = {http://www.altera.com/support/software/system/sopc/sof-sopc\_builder.html},
98	year = {2009},
99	}
100
101	@InProceedings{cosy,
102	author = { J.Y Brunel, al },
103	title = { COSY: a methodology for system design based on reusable hardware \& software IP's},
104	booktitle = { Technologies for the Information Society },
105	publisher = { IOS Press },
106	year = {1998},
107	pages = {709-716},
108	}
109
110	@InProceedings{disydent05,
111	author = {{Ivan Aug\'{e}, Fr\'{e}d\'{e}ric P\'{e}trot, Fran\c{c}ois Donnet and Pascal Gomez}},
112	title = {{Platform-based design from parallel C specifications}},
113	booktitle = {IEEE Transaction on CAD of Integrated Circuits and Systems},
114	pages = {1811--1826},
115	month = {December},
116	year = {2005},
117	}
118	@inproceedings{dspin08,
119	author = {Miro-Panades, Ivan and Clermidy, Fabien and Vivet, Pascal and Greiner, Alain},
120	title = {Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture},
121	booktitle = {NOCS '08: Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip},
122	year = {2008},
123	isbn = {978-0-7695-3098-7},
124	pages = {139--148},
125	publisher = {IEEE Computer Society},
126	address = {Washington, DC, USA},
127	}
128
129
130	% HLS
131	% http://mesl.ucsd.edu/spark/index.shtml
132	@INBOOK{spark04,
133	author = {S. Gupta and al.},
134	title = {SPARK: A Parallelizing Approach to the High-Level Synthesis of Digital Circuits},
135	publisher = {Springer},
136	year = {2004},
137	}
138
139
140	@INBOOK{ugh08,
141	author = {Ivan Aug\'{e} and Fr\'{e}d\'{e}ric P\'{e}trot},
142	title = {User Guided High Level Synthesis},
143	booktitle = {High-Level Synthesis: From Algorithm to Digital Circuits},
144	publisher = {Springer},
145	year = {2008},
146	chapter = {10},
147	pages = {139-148},
148	}
149	%editor = { Philippe Coussy and Adam Moriawiec},
150
151	@misc{pico,
152	title = {{PICO}},
153	howpublished = {http://www.synfora.com/},
154	year = {2009},
155	}
156
157	@misc{catapult-c,
158	title = {{CATAPULT-C Mentor HLS tool}},
159	howpublished = {http://www.mentor.com/products/esl/high\_level\_synthesis/},
160	year = {2009},
161	}
162
163	@misc{cynthetizer,
164	title = {{Forte's CYNTHESIZER}},
165	howpublished = {http://www.forteds.com/},
166	year = {2009},
167	}
168
169	@inproceedings{IP-XACT-08,
170	author = {Kruijtzer, Wido and van der Wolf, Pieter and de Kock, Erwin and Stuyt, Jan and Ecker, Wolfgang and Mayer, Albrecht and Hustin, Serge and Amerijckx, Christophe and de Paoli, Serge and Vaumorin, Emmanuel},
171	title = {Industrial IP integration flows based on IP-XACT standards},
172	booktitle = {Proceedings of the conference on Design, automation and test in Europe},
173	series = {DATE '08},
174	year = {2008},
175	isbn = {978-3-9810801-3-1},
176	location = {Munich, Germany},
177	pages = {32--37},
178	numpages = {6},
179	url = {http://doi.acm.org/10.1145/1403375.1403386},
180	doi = {http://doi.acm.org/10.1145/1403375.1403386},
181	acmid = {1403386},
182	publisher = {ACM},
183	address = {New York, NY, USA},
184	}
185
186
187	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
188	%%% UBS
189
190	@INBOOK{IEEEDT,
191	author = {Philippe Coussy and Andres Takach},
192	title = {Special Issue on High-Level Synthesis},
193	journal ={IEEE Design and Test of Computers},
194	volume = {25},issn = {0740-7475},
195	year = {2008},
196	pages = {393},doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2008.147},
197	publisher = {IEEE Computer Society},
198	address = {Los Alamitos, CA, USA},}
199
200
201	@INBOOK{HLSBOOK,
202	author = {P. Coussy and A. Morawiec},
203	booktitle = {High-Level Synthesis: From Algorithm to Digital Circuits},
204	publisher = {Springer},
205	year = {2008},
206	}
207
208	@INBOOK{CATRENE,
209	author = {CATRENE, Cluster for Application and Technology Research in Europe on NanotElectronics},
210	booktitle = {European Roadmap for EDA},
211	publisher = {CATRENE, Cluster for Application and Technology Research in Europe on NanotElectronics},
212	year = {2009},
213	}
214
215	@INBOOK{gaut08,
216	author = {P. Coussy and al.},
217	title = {GAUT: A High-Level Synthesis Tool for DSP applications},
218	booktitle = {High-Level Synthesis: From Algorithm to Digital Circuits},
219	publisher = {Springer},
220	year = {2008},
221	}
222
223	@article{DBLP:journals/dt/CoussyT09,
224	author = {Philippe Coussy and
225	Andres Takach},
226	title = {Guest Editors' Introduction: Raising the Abstraction Level
227	of Hardware Design},
228	journal = {IEEE Design {\&} Test of Computers},
229	volume = {26},
230	number = {4},
231	year = {2009},
232	pages = {4-6},
233	ee = {http://doi.ieeecomputersociety.org/10.1109/MDT.2009.80},
234	bibsource = {DBLP, http://dblp.uni-trier.de}
235	}
236
237
238	@article{DBLP:journals/dt/CoussyGMT09,
239	author = {Philippe Coussy and
240	Daniel D. Gajski and
241	Michael Meredith and
242	Andres Takach},
243	title = {An Introduction to High-Level Synthesis},
244	journal = {IEEE Design {\&} Test of Computers},
245	volume = {26},
246	number = {4},
247	year = {2009},
248	pages = {8-17},
249	ee = {http://doi.ieeecomputersociety.org/10.1109/MDT.2009.69},
250	bibsource = {DBLP, http://dblp.uni-trier.de}
251	}
252
253
254	@article{DBLP:journals/vlsisp/ThabetCHM09,
255	author = {Farhat Thabet and
256	Philippe Coussy and
257	Dominique Heller and
258	Eric Martin},
259	title = {Exploration and Rapid Prototyping of DSP Applications using
260	SystemC Behavioral Simulation and High-level Synthesis},
261	journal = {Signal Processing Systems},
262	volume = {56},
263	number = {2-3},
264	year = {2009},
265	pages = {167-186},
266	ee = {http://dx.doi.org/10.1007/s11265-008-0235-1},
267	bibsource = {DBLP, http://dblp.uni-trier.de}
268	}
269
270
271
272	@inproceedings{CHAVET:2007:HAL-00153994:1,
273	title = { {A} {M}ethodology for {E}fficient {S}pace-{T}ime {A}dapter {D}esign {S}pace {E}xploration: {A} {C}ase {S}tudy of an {U}ltra {W}ide {B}and {I}nterleaver},
274	author = {{C}havet, {C}yrille and {C}oussy, {P}hilippe and {U}rard, {P}ascal and {M}artin, {E}ric},
275	abstract = {{T}his paper presents a solution to efficiently explore the design space of communication adapters. {I}n most digital signal processing ({DSP}) applications, the overall architecture of the system is significantly affected by communication architecture, so the designers need specifically optimized adapters. {B}y explicitly modeling these communications within an effective graph-theoretic model and analysis framework, we automatically generate an optimized architecture, named {S}pace-{T}ime {A}dapte{R} ({STAR}). {O}ur design flow inputs a {C} description of {I}nput/{O}utput data scheduling, and user requirements (throughput, latency, parallelism...), and formalizes communication constraints through a {R}esource {C}onstraints {G}raph ({RCG}). {T}he {RCG} properties enable an efficient architecture space exploration in order to synthesize a {STAR} component. {T}he proposed approach has been tested to design an industrial data mixing block example: an {U}ltra-{W}ideband interleaver.},
276	language = {{A}nglais},
277	affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud - {STM}icroelectronics - {STM} - {STM}icroelectronics },
278	booktitle = {{P}roceedings of the {IEEE} {I}nternational {S}ymposium on {C}ircuits and {S}ystems ({ISCAS}) {T}he {IEEE} {I}nternational {S}ymposium on {C}ircuits and {S}ystems ({ISCAS}) },
279	publisher = {{L}ibrary of {C}ongress },
280	pages = {2946 },
281	address = {{N}ew {O}rleans {\'E}tats-{U}nis d'{A}m{\'e}rique },
282	editor = {{IEEE} },
283	note = {{ISBN}:1-4244-0921-7 },
284	audience = {internationale },
285	day = {28},
286	month = {05},
287	year = {2007},
288	URL = {http://hal.archives-ouvertes.fr/hal-00153994/en/},
289	URL = {http://hal.archives-ouvertes.fr/hal-00153994/PDF/ISCAS_Chavet1992.pdf},
290	}
291
292
293	@inproceedings{DBLP:conf/iccad/ChavetACCJUM07,
294	author = {Cyrille Chavet and
295	Caaliph Andriamisaina and
296	Philippe Coussy and
297	Emmanuel Casseau and
298	Emmanuel Juin and
299	Pascal Urard and
300	Eric Martin},
301	title = {A design flow dedicated to multi-mode architectures for
302	DSP applications},
303	booktitle = {ICCAD},
304	year = {2007},
305	pages = {604-611},
306	ee = {http://doi.acm.org/10.1145/1326073.1326199},
307	crossref = {DBLP:conf/iccad/2007},
308	bibsource = {DBLP, http://dblp.uni-trier.de}
309	}
310
311
312	@inproceedings{DBLP:conf/glvlsi/ChavetCUM07,
313	author = {Cyrille Chavet and
314	Philippe Coussy and
315	Pascal Urard and
316	Eric Martin},
317	title = {A design methodology for space-time adapter},
318	booktitle = {ACM Great Lakes Symposium on VLSI},
319	year = {2007},
320	pages = {347-352},
321	ee = {http://doi.acm.org/10.1145/1228784.1228868},
322	crossref = {DBLP:conf/glvlsi/2007},
323	bibsource = {DBLP, http://dblp.uni-trier.de}
324	}
325
326
327	@inproceedings{CHAVET:2007:HAL-00154025:1,
328	title = { {A}pplication of a design space exploration tool to enhance interleaver generation},
329	author = {{C}havet, {C}yrille and {C}oussy, {P}hilippe and {U}rard, {P}ascal and {M}artin, {E}ric},
330	abstract = {{T}his paper presents a methodology to efficiently explore the design space of communication adapters. {I}n most digital signal processing ({DSP}) applications, the overall performance of the system is significantly affected by communication architectures, as a consequence the designers need specifically optimized adapters. {B}y explicitly modeling these communications within an effective graph-theoretic model and analysis framework, we automatically generate an optimized architecture, named {S}pace-{T}ime {A}dapte{R} ({STAR}). {O}ur design flow inputs a {C} description of {I}nput/{O}utput data scheduling, and user requirements (throughput, latency, parallelism...), and formalizes communication constraints through a {R}esource {C}onstraints {G}raph ({RCG}). {D}esign space exploration is then performed through associated tools, to synthesize a {STAR} component under time-to-market constraints. {T}he proposed approach has been tested to design an industrial data mixing block example: an {U}ltra-{W}ideband interleaver.},
331	language = {{A}nglais},
332	affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud - {STM}icroelectronics - {STM} - {STM}icroelectronics },
333	booktitle = {{P}roceedings of the {E}uropean {S}ignal {P}rocessing {C}onference ({EUSIPCO}-2007) {E}uropean {S}ignal {P}rocessing {C}onference ({EUSIPCO}-2007) },
334	publisher = {{E}urasip },
335	pages = {??? },
336	address = {{P}oznan {P}ologne },
337	audience = {internationale },
338	day = {03},
339	month = {09},
340	year = {2007},
341	URL = {http://hal.archives-ouvertes.fr/hal-00154025/en/},
342	URL = {http://hal.archives-ouvertes.fr/hal-00154025/PDF/EUSIPCO_chavet.pdf},
343	}
344
345
346	@inproceedings{ANDRIAMISAINA:2007:HAL-00153086:1,
347	title = { {S}ynthesis of {M}ultimode digital signal processing systems},
348	author = {{A}ndriamisaina, {C}aaliph and {C}asseau, {E}mmanuel and {C}oussy, {P}hilippe},
349	abstract = {{I}n this paper, we propose a design methodology for implementing a multimode (or multi-configuration) and multi-throughput system into a single hardware architecture. {T}he inputs of the design flow are the data flow graphs ({DFG}s), representing the different modes (i.e. the different applications to be implemented), with their respective throughput constraints. {W}hile traditional approaches merge {DFG}s together before the synthesis process, we propose to use ad-hoc scheduling and binding steps during the synthesis of each {DFG}. {T}he scheduling, which assigns operations to specific time steps, maximizes the similarity between the control steps and thus decreases the controller complexity. {T}he binding process, which assigns operations to specific functional units and data to specific storage elements, maximizes the similarity between datapaths and thus minimizes steering logic and register overhead. {F}irst results show the interest of the proposed synthesis flow.},
350	language = {{A}nglais},
351	affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud - {R}2{D}2 - {INRIA} - {IRISA} - {CNRS} : {UMR}6074 - {INRIA} - {I}nstitut {N}ational des {S}ciences {A}ppliqu{\'e}es de {R}ennes - {E}cole {N}ationale {S}up{\'e}rieure des {S}ciences {A}ppliqu{\'e}es et de {T}echnologie - {U}niversit{\'e} de {R}ennes 1 },
352	booktitle = {{P}roceeding of {A}daptive {H}ardware and {S}ystems {NASA}/{ESA} {C}onference on {A}daptive {H}ardware and {S}ystems },
353	publisher = {{AHS} },
354	pages = {7 },
355	address = {{E}dinburgh {R}oyaume-{U}ni },
356	audience = {internationale },
357	year = {2007},
358	URL = {http://hal.archives-ouvertes.fr/hal-00153086/en/},
359	URL = {http://hal.archives-ouvertes.fr/hal-00153086/PDF/PID411805.pdf},
360	}
361
362
363	@inproceedings{COUSSY:2005:HAL-00077301:1,
364	title = { {A} {M}ore {E}fficient and {F}lexible {DSP} {D}esign {F}low from {MATLAB}-{SIMULINK}},
365	author = {{C}oussy, {P}hilippe and {C}orre, {G}wenol{\'e} and {B}omel, {P}ierre and {S}enn, {E}ric and {M}artin, {E}ric},
366	abstract = {{T}he design of complex {D}igital {S}ignal {P}rocessing systems implies to minimize architectural cost and to maximize timing performances while taking into account communication and memory accesses constraints for the integration of dedicated hardware accelerator. {U}nfortunately, the traditional {M}atlab/{S}imulink design flows gather not very flexible hardware blocs. {I}n this paper, we present a methodology and a tool that permit the {H}igh-{L}evel {S}ynthesis of {DSP} applications, under both {I}/{O} timing and memory constraints. {B}ased on formal models and a generic architecture, this tool helps the designer in finding a reasonable trade-off between the circuit's latency and its architectural complexity. {T}he efficiency of our approach is demonstrated on the case study of a {FFT} algorithm.},
367	keywords = {{DSP} application, synthesis under memory and communication constraints},
368	language = {{A}nglais},
369	affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud },
370	booktitle = {{IEEE} {I}nternational {C}onference on {A}coustic, {S}peech and {S}ignal {P}rocessing },
371	publisher = {{IEEE} },
372	pages = {{V}ol. {V} p. 61-64 },
373	editor = {{IEEEE} },
374	year = {2005},
375	URL = {http://hal.archives-ouvertes.fr/hal-00077301/en/},
376	URL = {http://hal.archives-ouvertes.fr/hal-00077301/PDF/coussy_final.pdf},
377	}
378
379
380
381	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
382	%%%%% IRISA
383	@InProceedings{KluterCodes08,
384	author = {{Theo Kluter and Philip Brisk and Paolo Ienne and and Edoardo Charbon}},
385	title = {{Speculative DMA for Architecturally Visible Storage in Instruction Set Extensions}},
386	booktitle = {ISSS/CODES},
387	year = {2008},
388	}
389
390	@InProceedings{KluterDAC09,
391	author = {{Theo Kluter and Philip Brisk and Paolo Ienne and and Edoardo Charbon}},
392	title = {{Way Stealing : Cache-assisted Automatic Instruction Set Extensions}},
393	booktitle = {Design Automation Conference (DAC)},
394	year = {2009},
395	}
396
397	@InProceedings{YuCodes04,
398	author = {{Pan Yu and Tulika Mitra}},
399	title = {{Scalable Custom Instructions Identification for Instruction Set Extensible Processors}},
400	booktitle = {ISSS/CODES},
401	year = {2004},
402	}
403
404	@InProceedings{Dinh08,
405	author = {{Quang Dinh and Deming Chen and Martin D.~F.~Wong}},
406	title = {{Efficient ASIP Design for Configurable Processors with Fine-Grained Resource Sharing}},
407	booktitle = {ACM Internatibnal Conference Field Programmable Gate Arrays (FPGA)},
408	year = {2008},
409	}
410
411	@Misc{NIOS2UG,
412	title = {{Nios II Custom Instruction User Guide, Altera Corp.}},
413	year = {2008},
414	}
415
416	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
417	%%% CITI
418	@book{Polis,
419	author = {Balarin, Felice},
420	publisher = {Kluwer Academic Publishers},
421	title = {Hardware-software co-design of embedded systems : the POLIS
422	approach},
423	year = {1997}
424	}
425
426	@INPROCEEDINGS{Coware,
427	author = {Ivo Bolsens and Hugo J. De Man and Bill Lin and Karl Van
428	Rompaey and Steven Vercauteren and Diederik Verkest},
429	title = {Hardware/Software Co-Design of Digital Telecommunication Systems},
430	booktitle = {Proceedings of the IEEE},
431	year = {1997},
432	pages = {391--418}
433	}
434
435	@article{Jantsch,
436	author = {Mattias O'Nil and Axel Jantsch},
437	title = {Device Driver and DMA Controller Synthesis from HW/SW
438	Communication protocol specifications},
439	journal = {Design Automation for Embedded Systems},
440	year = {2001},
441	volume = {6},
442	pages = {177-205}
443	}
444
445	@InProceedings{Park01,
446	author = {Joonseok Park and Pedro C.~Diniz},
447	title = {Synthesis of Pipelined Memory Access Controllers for Streamed
448	Data Applications on {FPGA}-Based Computing Engines},
449	booktitle = {International Symposium on System Synthesis (ISSS)},
450	pages = {221-226},
451	year = {2001},
452	}
453
454	@article{FR-vlsi,
455	author = {Antoine Fraboulet and Tanguy Risset},
456	title = {Master Interface for On-Chip Hardware Accelerator Burst Communications},
457	journal = {Journal of VLSI Signal Processing},
458	publisher = {Springer Science},
459	year = {2007},
460	volume = {59},
461	pages = {73-85}
462	}
463
464	@InProceedings{jerraya,
465	author = {Sungjoo Yoo and Jerraya Ahmed},
466	title = {Introduction to Hardware Abstraction Layers for SoC},
467	OPTcrossref = {},
468	OPTkey = {},
469	booktitle = {Design, Automation and Test in Europe Conference and Exhibition},
470	pages = {336 -- 337},
471	year = 2003,
472	OPTeditor = {},
473	OPTvolume = {},
474	OPTnumber = {},
475	OPTseries = {},
476	OPTaddress = {},
477	OPTmonth = {},
478	OPTorganization = {},
479	OPTpublisher = {},
480	OPTnote = {},
481	OPTannote = {}
482	}
483
484	@INPROCEEDINGS{FAUST,
485	author = {D. Lattard and E. Beigne and C. Bernard and C. Bour and F.
486	Clermidy and Y. Durand and J. Durupt and D. Varreau and P. Vivet and
487	P. Penard and A. Bouttier and F. Berens},
488	title = "A Telecom Baseband Circuit-Based on an Asynchronous Network-on-Chip",
489	pages = {},
490	BOOKTITLE="ISSCC\'2007",
491	year = {2007},
492	publisher = {IEEE Computer Society},
493	address = {San Francisco, USA},
494	};
495
496	@inproceedings{JerrayaPetrot,
497	author = {Ahmed A. Jerraya and Aimen Bouchhima and Fr\'{e}d\'{e}ric P\'{e}trot},
498	title = {Programming models and HW-SW interfaces abstraction for multi-processor SoC},
499	booktitle = {DAC '06: Proceedings of the 43rd annual conference on Design automation},
500	year = {2006},
501	isbn = {1-59593-381-6},
502	pages = {280--285},
503	location = {San Francisco, CA, USA},
504	publisher = {ACM},
505	address = {New York, NY, USA},
506	}
507
508	@inproceedings{mwmr,
509	author = {E. Faure and A. Greiner and D. Genius},
510	title = {A generic hardware/software communication mechanism for
511	Multi-Processor System on Chip, Targeting Telecommunication Applications},
512	booktitle = {ReCoSoC'06},
513	year = {2006},
514	pages = {237--242},
515	address = {Montpellier, France}
516	}
517
518	@inproceedings{Alberto,
519	author = {Roberto Passerone and
520	James A. Rowson and
521	Alberto L. Sangiovanni-Vincentelli},
522	title = {Automatic Synthesis of Interfaces Between Incompatible Protocols},
523	booktitle = {DAC},
524	year = {1998},
525	pages = {8-13}
526	}
527
528	@article{Avnit,
529	author = {Karin Avnit and
530	Vijay D'Silva and
531	Arcot Sowmya and
532	S. Ramesh and
533	Sri Parameswaran},
534	title = {Provably correct on-chip communication: A formal approach
535	to automatic protocol converter synthesis},
536	journal = {ACM Trans. Design Autom. Electr. Syst.},
537	volume = {14},
538	number = {2},
539	year = {2009}
540	}
541
542	@inproceedings{smith,
543	author = {James Smith and
544	Giovanni De Micheli},
545	title = {Automated Composition of Hardware Components},
546	booktitle = {DAC},
547	year = {1998},
548	pages = {14-19}
549	}
550
551	@inproceedings{Narayan,
552	author = {Sanjiv Narayan and
553	Daniel Gajski},
554	title = {Interfacing Incompatible Protocols Using Interface Process
555	Generation},
556	booktitle = {DAC},
557	year = {1995},
558	pages = {468-473}
559	}
560
561	@TECHREPORT{Ptolemy,
562	AUTHOR = { E.A. Lee et al.},
563	INSTITUTION = {University of California, Berkeley},
564	NUMBER = {UCB/ERL No. M99/37},
565	TITLE = {Overview of the Ptolemy Project},
566	YEAR = {1999},
567	MONTH = {july}
568	}
569
570	@article{syntol,
571	author={Paul Feautrier},
572	title={Scalable and Structured Scheduling},
573	journal={Int. J. of Parallel Programming},
574	year=2006,
575	month=May, number=5, volume=34,
576	pages="459--487"
577	}
578
579	@InProceedings{bee,
580	author={Christophe Alias and Fabrice Baray and Alain Darte},
581	title={Bee+Cl@k: An Implementation of Lattice-Based Array Contraction in the Source-to-Source Translator ROSE},
582	booktitle = {LCTES},
583	year = {2007},
584	publisher = {ACM}
585	}
586
587	%%%%%%%%%%%%% ASIP %%%%%%%%%%%%%%%%
588
589	@inproceedings{DAC09,
590	author = {Kluter, Theo and Brisk, Philip and Ienne, Paolo and Charbon, Edoardo},
591	title = {Way Stealing: cache-assisted automatic instruction set extensions},
592	booktitle = {DAC '09: Proceedings of the 46th Annual Design Automation Conference},
593	year = {2009},
594	isbn = {978-1-60558-497-3},
595	pages = {31--36},
596	location = {San Francisco, California},
597	doi = {http://doi.acm.org/10.1145/1629911.1629923},
598	publisher = {ACM},
599	address = {New York, NY, USA},
600	}
601
602	@inproceedings{CODES08,
603	author = {Kluter, Theo and Brisk, Philip and Ienne, Paolo and Charbon, Edoardo},
604	title = {Speculative DMA for architecturally visible storage in instruction set extensions},
605	booktitle = {CODES/ISSS '08: Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis},
606	year = {2008},
607	isbn = {978-1-60558-470-6},
608	pages = {243--248},
609	location = {Atlanta, GA, USA},
610	doi = {http://doi.acm.org/10.1145/1450135.1450191},
611	publisher = {ACM},
612	address = {New York, NY, USA},
613	}
614
615	@article{TVLSI06,
616	author = {Cong, Jason and Han, Guoling and Zhang, Zhiru},
617	title = {Architecture and compiler optimizations for data bandwidth improvement in configurable processors},
618	journal = {IEEE Trans. Very Large Scale Integr. Syst.},
619	volume = {14},
620	number = {9},
621	year = {2006},
622	issn = {1063-8210},
623	pages = {986--997},
624	doi = {http://dx.doi.org/10.1109/TVLSI.2006.884050},
625	publisher = {IEEE Educational Activities Department},
626	address = {Piscataway, NJ, USA},
627	}
628
629
630	@Book{NIOS2,
631	title = {{Nios II Processor Reference Handbook}},
632	publisher = {Altera},
633	year = {2009},
634	}
635
636
637	@inproceedings{ARC08,
638	author = {Galuzzi, Carlo and Bertels, Koen},
639	title = {The Instruction-Set Extension Problem: A Survey},
640	booktitle = {ARC '08: Proceedings of the 4th international workshop on Reconfigurable Computing},
641	year = {2008},
642	isbn = {978-3-540-78609-2},
643	pages = {209--220},
644	location = {London, UK},
645	doi = {http://dx.doi.org/10.1007/978-3-540-78610-8_21},
646	publisher = {Springer-Verlag},
647	address = {Berlin, Heidelberg},
648	}
649
650	@inproceedings{CODES99,
651	author = {Charot, Fran\c{c}ois and Mess\'{e}, Vincent},
652	title = {{A flexible code generation framework for the design of application specific programmable processors}},
653	booktitle = {CODES '99: Proceedings of the seventh international workshop on Hardware/software codesign},
654	year = {1999},
655	pages = {27--31},
656	location = {Rome, Italy},
657	publisher = {ACM},
658	address = {New York, NY, USA},
659	}
660
661	@inproceedings{ASAP05,
662	author = {L'Hours, Ludovic},
663	title = {{Generating Efficient Custom FPGA Soft-Cores for Control-Dominated Applications}},
664	booktitle = {ASAP '05: Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors},
665	year = {2005},
666	pages = {127--133},
667	publisher = {IEEE Computer Society},
668	address = {Washington, DC, USA},
669	}
670
671	@inproceedings{roma,
672	author = {Menard, Daniel and Casseau, Emmanuel and Khan, Shafqat and Sentieys, Olivier and Chevobbe, St\'{e}phane and Guyetant, St\'{e}phane and David, Raphael},
673	title = {Reconfigurable Operator Based Multimedia Embedded Processor},
674	booktitle = {ARC '09: Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications},
675	year = {2009},
676	pages = {39--49},
677	location = {Karlsruhe, Germany},
678	publisher = {Springer-Verlag},
679	address = {Berlin, Heidelberg},
680	}
681
682	%%%%%%%%%%%%% AUTRES %%%%%%%%%%%%%%%%
683
684	@inproceedings{thales-viola,
685	author = {Viola, Jones},
686	title = {{Rapid Object Detection using a Boosted Cascade of Simple Feature}},
687	booktitle = {Proceedings of Conference on Computer Vision and Pattern recognition},
688	year = {2001},
689	}
690	@INPROCEEDINGS{FP:96
691	,AUTHOR = "Paul Feautrier"
692	,TITLE = "Automatic Parallelization in the Polytope Model"
693	,BOOKTITLE = "The Data-Parallel Programming Model"
694	,YEAR = 1996
695	,EDITOR = "Guy-Ren\'e Perrin and Alain Darte"
696	,PAGES = "79--103"
697	,VOLUME = "LNCS 1132"
698	,PUBLISHER = "Springer"
699	}
700
701	@book{DRV:2000,
702	author={Alain Darte and Yves Robert and Fr\'ed\'eric Vivien},
703	title={Scheduling and automatic Parallelization},
704	publisher={Birkh\"auser}, year=2000
705	}
706
707	@Article{Feau:92aa,
708	author = "Paul Feautrier",
709	title = "Some Efficient Solutions to the Affine Scheduling
710	Problem, {I}, One Dimensional Time",
711	volume = "21",
712	number = "5",
713	month = Oct,
714	pages = "313--348",
715	journal = "Int. J. of Parallel Programming",
716	year = "1992"
717	}
718
719	@Article{Feau:92bb,
720	author = "Paul Feautrier",
721	title = "Some Efficient Solutions to the Affine Scheduling
722	Problem, {II}, Multidimensional Time",
723	volume = "21",
724	number = "6",
725	journal = "Int. J. of Parallel Programming",
726	month = Dec,
727	pages = "389--420",
728	year = "1992"
729	}
730
731	@ARTICLE{Feau:96
732	,AUTHOR = {Paul Feautrier}
733	,TITLE = {Distribution Automatique des Donn\'es et des
734	calculs}
735	,JOURNAL = {T.S.I.}
736	,YEAR = 1996, VOLUME = 15, NUMBER = 5, PAGES = {529--557}
737	}
738
739	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
740	%%% IA
741
742	@PHDTHESIS{ia-hdr-phd,
743	author = {Ivan Aug\'{e}},
744	title = {Th\`ese d'Habilitation \`a Diriger des Recherches:
745	Synth\`ese de haut niveau \& Int\'egration
746	des syst\`emes mat\'eriel/logiciel},
747	school = {Universit\'e Pierre et Marie Curie},
748	year = {2009},
749	month = {12},
750	}
751
752	@MISC{ia-hdr,
753	author = {Ivan Aug\'{e}},
754	title = {Th\`ese d'Habilitation \`a Diriger des Recherches:
755	Synth\`ese de haut niveau \& Int\'egration
756	des syst\`emes mat\'eriel/logiciel},
757	howpublished = {Universit\'e Pierre et Marie Curie},
758	year = {2009},
759	month = {12},
760	}
761
762	@INBOOK{ia-ugh08,
763	author = {Ivan Aug\'{e} and Fr\'{e}d\'{e}ric P\'{e}trot},
764	title = {User Guided High Level Synthesis},
765	booktitle = {High-Level Synthesis: From Algorithm to Digital Circuits},
766	publisher = {Springer},
767	chapter = {10},
768	year = {2008},
769	pages = {139-148},
770	}
771	%editor = {Philippe Coussy and Adam Moriawiec},
772
773	@misc{ia-ugh-09-aspdac,
774	author = {Fr\'ed\'eric P\'etrot and Ivan Aug\'e},
775	title = {User Guided High Level Synthesis},
776	booktitle= {Workshop "High-Level Synthesis: Next Step to Efficient ESL Design",
777	in conjunction with ASP-DAC},
778	year = {2009},
779	}
780
781	@misc{ia-ugh-08-date,
782	author = {Fr\'ed\'eric P\'etrot and Ivan Aug\'e},
783	title = {User Guided High Level Synthesis},
784	booktitle= { Workshop "The New Wave of the High-Level Synthesis",
785	in conjunction with DATE},
786	year = {2008},
787	}
788
789	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
790	%%% AG
791
792	@article{ag-1,
793	author = {Zhen Zhang and Alain Greiner and Mounir Benabdenbi},
794	title = {Fully distributed initialization procedure for a 2D-Mesh NoC, including off-line BIST and partial deactivation of faulty components},
795	journal ={On-Line Testing Symposium, IEEE International},
796	volume = {0},
797	isbn = {978-1-4244-7724-1},
798	year = {2010},
799	pages = {194-196},
800	doi = {http://doi.ieeecomputersociety.org/10.1109/IOLTS.2010.5560209},
801	publisher = {IEEE Computer Society},
802	address = {Los Alamitos, CA, USA},
803	}
804
805	@inproceedings{ag-2,
806	author = {Greiner Alain and Faure Etienne and Pouillon Nicolas and Genius Dani\'ela},
807	title = {A Generic Hardware/Software Communication Middleware for
808	Streaming Applications on Shared Memory Multi Processor Systems-on-Chip},
809	booktitle = {Forum on Specification \& Design Languages (FDL 2009)},
810	isbn = { 978-2-9530504-1-7},
811	month = {September},
812	year = {2009},
813	address = {Nice, France},
814	}
815
816	@inproceedings{ag-3,
817	author = {Porquet, Jo\"{e}l and Schwarz, Christian and Greiner, Alain},
818	title = {Multi-compartment: A new architecture for secure
819	co-hosting on SoC },
820	booktitle = {Proceedings of the 11th international conference on System-on-chip},
821	series = {SOC'09},
822	month = {October},
823	year = {2009},
824	isbn = {978-1-4244-4466-3},
825	location = {Tampere, Finland},
826	pages = {124-127},
827	numpages = {4},
828	url = {http://portal.acm.org/citation.cfm?id=1736530.1736555},
829	publisher = {IEEE Press},
830	address = {Piscataway, NJ, USA},
831	}
832
833	@inproceedings{ag-4,
834	author = {Miro-Panades, Ivan and Clermidy, Fabien and Vivet, Pascal and Greiner, Alain},
835	title = {Physical Implementation of the DSPIN Network-on-Chip in the
836	FAUST Architecture},
837	booktitle = {Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip},
838	series = {NOCS'08},
839	year = {2008},
840	month = {April},
841	isbn = {978-0-7695-3098-7},
842	location = {Newcastle, UK},
843	pages = {139-148},
844	numpages = {10},
845	url = {http://portal.acm.org/citation.cfm?id=1397757.1397994},
846	publisher = {IEEE Computer Society},
847	address = {Washington, DC, USA},
848	}
849
850
851
852	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
853	%%% XXXX
854

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