source: anr/anr.bib @ 174

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Paul: Addition de deux references
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1%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
2%%%%% LIP6
3% HPC
4@InProceedings{hpc06a,
5  author    = {{M.B. Gokhale and al.}},
6  title     = {{Promises and Pitfalls of Reconfigurable Supercomputing}},
7  booktitle = {Systems and Algorithms, CSREA Press},
8  pages     = {11-20},
9  year      = {2006},
10}
11@MISC{hpc06b,
12  author =       {{D. Buell}},
13  title  =   {{Programming Reconfigurable Computers}},
14  booktitle = {Summer Institute},
15  howpublished = {http://gladiator.ncsa.uiuc.edu/PDFs/rssi06/presentations/00\_Duncan\_Buell.pdf},
16  year =         {2006},
17}
18@InProceedings{hpc07a,
19  author =       {{T. Van Court and al.}},
20  title  =   {{ Achieving High Performance with FPGA-Based Computing}},
21  booktitle = {Computer, vol. 40, no. 3},
22  pages     = {50-57},
23  month     = {mars},
24  year =         {2007},
25}
26@misc{hpc08,
27  title        = {Mitrionics},
28  howpublished = {http://www.mitrionics.com/},
29  year         = {2009},
30}
31@misc{hpc09,
32  title        = {Gidel},
33  howpublished = {http://www.gidel.com/},
34  year         = {2009},
35}
36@misc{hpc10,
37  title        = {Convey Computer},
38  howpublished = {http://www.conveycomputers.com/},
39  year         = {2009},
40}
41@InProceedings{hpc11,
42  author =      {E. El-Araby, I. Gonzalez and T. El-Ghazawi},
43  title   = {Virtual Architecture and Design Automation for Partial Reconfiguration },
44  booktitle = {HPRCTA},
45  year =         {2008},
46}
47@InProceedings{hpc12,
48  author =       {{P. Lysaght and J. Dunlop}},
49  title   = {Dynamic Reconfiguration of Field Programmable Gate Arrays},
50  booktitle = {Field Programmable Logic and Applications, Oxford, England},
51  month     = {Sept},
52  year =         {1993},
53}
54
55
56% System design
57@misc{soclib,
58  title        = {Soclib},
59  howpublished = {http://www.soclib.fr/},
60  year         = {2009},
61}
62
63@misc{system-generateur-for-dsp,
64  title        = {{System Generator for DSP}},
65  howpublished = {http://www.xilinx.com/tools/sysgen.htm},
66  year         = {2009},
67}
68
69@misc{spoc-builder,
70  title        = {{sopc builder support}},
71  howpublished = {http://www.altera.com/support/software/system/sopc/sof-sopc\_builder.html},
72  year         = {2009},
73}
74
75@InProceedings{cosy,
76    author = { J.Y Brunel, al },
77    title  = { COSY: a methodology for system design based on reusable hardware \& software IP's},
78    booktitle = { Technologies for the Information Society },
79    publisher = { IOS Press },
80    year      = {1998},
81    pages     = {709-716},
82}
83
84@InProceedings{disydent05,
85  author =       {{Ivan Aug\'{e}, Fr\'{e}d\'{e}ric P\'{e}trot, Franï¿œois Donnet and Pascal Gomez}},
86  title =        {{Platform-based design from parallel C specifications}},
87  booktitle = {IEEE Transaction on CAD of Integrated Circuits and Systems},
88  pages     = {1811--1826},
89  month     = {December},
90  year =         {2005},
91}
92@inproceedings{dspin08,
93 author = {Miro-Panades, Ivan and Clermidy, Fabien and Vivet, Pascal and Greiner, Alain},
94 title = {Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture},
95 booktitle = {NOCS '08: Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip},
96 year = {2008},
97 isbn = {978-0-7695-3098-7},
98 pages = {139--148},
99 publisher = {IEEE Computer Society},
100 address = {Washington, DC, USA},
101 }
102
103
104% HLS
105% http://mesl.ucsd.edu/spark/index.shtml
106@BOOK{spark04,
107  author     = {S. Gupta and al.},
108  title      = {SPARK: A Parallelizing Approach to the High-Level Synthesis of Digital Circuits},
109  publisher  = {Springer},
110  year       = {2004},
111}
112
113
114@INBOOK{ugh08,
115  author    = {Ivan Aug\'{e} and Fr\'{e}d\'{e}ric P\'{e}trot},
116  title     = {User Guided High Level Synthesis},
117  booktitle = {High-Level Synthesis: From Algorithm to Digital Circuits},
118  publisher = {Springer},
119  chapter   = {10},
120  year      = {2008},
121}
122
123@misc{pico,
124  title        = {{PICO}},
125  howpublished = {http://www.synfora.com/},
126  year         = {2009},
127}
128
129@misc{catapult-c,
130  title        = {{CATAPULT-C Mentor HLS tool}},
131  howpublished = {http://www.mentor.com/products/esl/high\_level\_synthesis/},
132  year         = {2009},
133}
134
135@misc{cynthetizer,
136  title        = {{Forte's CYNTHESIZER}},
137  howpublished = {http://www.forteds.com/},
138  year         = {2009},
139}
140
141
142
143%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
144%%% UBS
145
146
147@INBOOK{gaut08,
148  author    = {P. Coussy and al.},
149  title     = {GAUT: A High-Level Synthesis Tool for DSP applications},
150  booktitle = {High-Level Synthesis: From Algorithm to Digital Circuits},
151  publisher = {Springer},
152  year      = {2008},
153}
154
155@article{DBLP:journals/dt/CoussyT09,
156  author    = {Philippe Coussy and
157               Andres Takach},
158  title     = {Guest Editors' Introduction: Raising the Abstraction Level
159               of Hardware Design},
160  journal   = {IEEE Design {\&} Test of Computers},
161  volume    = {26},
162  number    = {4},
163  year      = {2009},
164  pages     = {4-6},
165  ee        = {http://doi.ieeecomputersociety.org/10.1109/MDT.2009.80},
166  bibsource = {DBLP, http://dblp.uni-trier.de}
167}
168
169
170@article{DBLP:journals/dt/CoussyGMT09,
171  author    = {Philippe Coussy and
172               Daniel D. Gajski and
173               Michael Meredith and
174               Andres Takach},
175  title     = {An Introduction to High-Level Synthesis},
176  journal   = {IEEE Design {\&} Test of Computers},
177  volume    = {26},
178  number    = {4},
179  year      = {2009},
180  pages     = {8-17},
181  ee        = {http://doi.ieeecomputersociety.org/10.1109/MDT.2009.69},
182  bibsource = {DBLP, http://dblp.uni-trier.de}
183}
184
185
186@article{DBLP:journals/vlsisp/ThabetCHM09,
187  author    = {Farhat Thabet and
188               Philippe Coussy and
189               Dominique Heller and
190               Eric Martin},
191  title     = {Exploration and Rapid Prototyping of DSP Applications using
192               SystemC Behavioral Simulation and High-level Synthesis},
193  journal   = {Signal Processing Systems},
194  volume    = {56},
195  number    = {2-3},
196  year      = {2009},
197  pages     = {167-186},
198  ee        = {http://dx.doi.org/10.1007/s11265-008-0235-1},
199  bibsource = {DBLP, http://dblp.uni-trier.de}
200}
201
202
203
204@inproceedings{CHAVET:2007:HAL-00153994:1,
205        title = { {A} {M}ethodology for {E}fficient {S}pace-{T}ime {A}dapter {D}esign {S}pace {E}xploration: {A} {C}ase {S}tudy of an {U}ltra {W}ide {B}and {I}nterleaver},
206        author = {{C}havet, {C}yrille and {C}oussy, {P}hilippe and {U}rard, {P}ascal and {M}artin, {E}ric},
207        abstract = {{T}his paper presents a solution to efficiently explore the design space of communication adapters. {I}n most digital signal processing ({DSP}) applications, the overall architecture of the system is significantly affected by communication architecture, so the designers need specifically optimized adapters. {B}y explicitly modeling these communications within an effective graph-theoretic model and analysis framework, we automatically generate an optimized architecture, named {S}pace-{T}ime {A}dapte{R} ({STAR}). {O}ur design flow inputs a {C} description of {I}nput/{O}utput data scheduling, and user requirements (throughput, latency, parallelism...), and formalizes communication constraints through a {R}esource {C}onstraints {G}raph ({RCG}). {T}he {RCG} properties enable an efficient architecture space exploration in order to synthesize a {STAR} component. {T}he proposed approach has been tested to design an industrial data mixing block example: an {U}ltra-{W}ideband interleaver.},
208        language = {{A}nglais},
209        affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud - {STM}icroelectronics - {STM} - {STM}icroelectronics },
210        booktitle = {{P}roceedings of the {IEEE} {I}nternational {S}ymposium on {C}ircuits and {S}ystems ({ISCAS}) {T}he {IEEE} {I}nternational {S}ymposium on {C}ircuits and {S}ystems ({ISCAS}) },
211        publisher = {{L}ibrary of {C}ongress },
212        pages = {2946 },
213        address = {{N}ew {O}rleans {\'E}tats-{U}nis d'{A}m{\'e}rique },
214        editor = {{IEEE} },
215        note = {{ISBN}:1-4244-0921-7 },
216        audience = {internationale },
217    day = {28},
218    month = {05},
219    year = {2007},
220    URL = {http://hal.archives-ouvertes.fr/hal-00153994/en/},
221    URL = {http://hal.archives-ouvertes.fr/hal-00153994/PDF/ISCAS_Chavet1992.pdf},
222}
223
224
225@inproceedings{DBLP:conf/iccad/ChavetACCJUM07,
226  author    = {Cyrille Chavet and
227               Caaliph Andriamisaina and
228               Philippe Coussy and
229               Emmanuel Casseau and
230               Emmanuel Juin and
231               Pascal Urard and
232               Eric Martin},
233  title     = {A design flow dedicated to multi-mode architectures for
234               DSP applications},
235  booktitle = {ICCAD},
236  year      = {2007},
237  pages     = {604-611},
238  ee        = {http://doi.acm.org/10.1145/1326073.1326199},
239  crossref  = {DBLP:conf/iccad/2007},
240  bibsource = {DBLP, http://dblp.uni-trier.de}
241}
242
243
244@inproceedings{DBLP:conf/glvlsi/ChavetCUM07,
245  author    = {Cyrille Chavet and
246               Philippe Coussy and
247               Pascal Urard and
248               Eric Martin},
249  title     = {A design methodology for space-time adapter},
250  booktitle = {ACM Great Lakes Symposium on VLSI},
251  year      = {2007},
252  pages     = {347-352},
253  ee        = {http://doi.acm.org/10.1145/1228784.1228868},
254  crossref  = {DBLP:conf/glvlsi/2007},
255  bibsource = {DBLP, http://dblp.uni-trier.de}
256}
257
258
259@inproceedings{CHAVET:2007:HAL-00154025:1,
260        title = { {A}pplication of a design space exploration tool to enhance interleaver generation},
261        author = {{C}havet, {C}yrille and {C}oussy, {P}hilippe and {U}rard, {P}ascal and {M}artin, {E}ric},
262        abstract = {{T}his paper presents a methodology to efficiently explore the design space of communication adapters. {I}n most digital signal processing ({DSP}) applications, the overall performance of the system is significantly affected by communication architectures, as a consequence the designers need specifically optimized adapters. {B}y explicitly modeling these communications within an effective graph-theoretic model and analysis framework, we automatically generate an optimized architecture, named {S}pace-{T}ime {A}dapte{R} ({STAR}). {O}ur design flow inputs a {C} description of {I}nput/{O}utput data scheduling, and user requirements (throughput, latency, parallelism...), and formalizes communication constraints through a {R}esource {C}onstraints {G}raph ({RCG}). {D}esign space exploration is then performed through associated tools, to synthesize a {STAR} component under time-to-market constraints. {T}he proposed approach has been tested to design an industrial data mixing block example: an {U}ltra-{W}ideband interleaver.},
263        language = {{A}nglais},
264        affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud - {STM}icroelectronics - {STM} - {STM}icroelectronics },
265        booktitle = {{P}roceedings of the {E}uropean {S}ignal {P}rocessing {C}onference ({EUSIPCO}-2007) {E}uropean {S}ignal {P}rocessing {C}onference ({EUSIPCO}-2007) },
266        publisher = {{E}urasip },
267        pages = {??? },
268        address = {{P}oznan {P}ologne },
269        audience = {internationale },
270    day = {03},
271    month = {09},
272    year = {2007},
273    URL = {http://hal.archives-ouvertes.fr/hal-00154025/en/},
274    URL = {http://hal.archives-ouvertes.fr/hal-00154025/PDF/EUSIPCO_chavet.pdf},
275}
276
277
278@inproceedings{ANDRIAMISAINA:2007:HAL-00153086:1,
279        title = { {S}ynthesis of {M}ultimode digital signal processing systems},
280        author = {{A}ndriamisaina, {C}aaliph and {C}asseau, {E}mmanuel and {C}oussy, {P}hilippe},
281        abstract = {{I}n this paper, we propose a design methodology for implementing a multimode (or multi-configuration) and multi-throughput system into a single hardware architecture. {T}he inputs of the design flow are the data flow graphs ({DFG}s), representing the different modes (i.e. the different applications to be implemented), with their respective throughput constraints. {W}hile traditional approaches merge {DFG}s together before the synthesis process, we propose to use ad-hoc scheduling and binding steps during the synthesis of each {DFG}. {T}he scheduling, which assigns operations to specific time steps, maximizes the similarity between the control steps and thus decreases the controller complexity. {T}he binding process, which assigns operations to specific functional units and data to specific storage elements, maximizes the similarity between datapaths and thus minimizes steering logic and register overhead. {F}irst results show the interest of the proposed synthesis flow.},
282        language = {{A}nglais},
283        affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud - {R}2{D}2 - {INRIA} - {IRISA} - {CNRS} : {UMR}6074 - {INRIA} - {I}nstitut {N}ational des {S}ciences {A}ppliqu{\'e}es de {R}ennes - {E}cole {N}ationale {S}up{\'e}rieure des {S}ciences {A}ppliqu{\'e}es et de {T}echnologie - {U}niversit{\'e} de {R}ennes 1 },
284        booktitle = {{P}roceeding of {A}daptive {H}ardware and {S}ystems {NASA}/{ESA} {C}onference on {A}daptive {H}ardware and {S}ystems },
285        publisher = {{AHS} },
286        pages = {7 },
287        address = {{E}dinburgh {R}oyaume-{U}ni },
288        audience = {internationale },
289    year = {2007},
290    URL = {http://hal.archives-ouvertes.fr/hal-00153086/en/},
291    URL = {http://hal.archives-ouvertes.fr/hal-00153086/PDF/PID411805.pdf},
292}
293
294
295@inproceedings{COUSSY:2005:HAL-00077301:1,
296        title = { {A} {M}ore {E}fficient and {F}lexible {DSP} {D}esign {F}low from {MATLAB}-{SIMULINK}},
297        author = {{C}oussy, {P}hilippe and {C}orre, {G}wenol{\'e} and {B}omel, {P}ierre and {S}enn, {E}ric and {M}artin, {E}ric},
298        abstract = {{T}he design of complex {D}igital {S}ignal {P}rocessing systems implies to minimize architectural cost and to maximize timing performances while taking into account communication and memory accesses constraints for the integration of dedicated hardware accelerator. {U}nfortunately, the traditional {M}atlab/{S}imulink design flows gather not very flexible hardware blocs. {I}n this paper, we present a methodology and a tool that permit the {H}igh-{L}evel {S}ynthesis of {DSP} applications, under both {I}/{O} timing and memory constraints. {B}ased on formal models and a generic architecture, this tool helps the designer in finding a reasonable trade-off between the circuit's latency and its architectural complexity. {T}he efficiency of our approach is demonstrated on the case study of a {FFT} algorithm.},
299        keywords = {{DSP} application, synthesis under memory and communication constraints},
300        language = {{A}nglais},
301        affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud },
302        booktitle = {{IEEE} {I}nternational {C}onference on {A}coustic, {S}peech and {S}ignal {P}rocessing },
303        publisher = {{IEEE} },
304        pages = {{V}ol. {V} p. 61-64 },
305        editor = {{IEEEE} },
306    year = {2005},
307    URL = {http://hal.archives-ouvertes.fr/hal-00077301/en/},
308    URL = {http://hal.archives-ouvertes.fr/hal-00077301/PDF/coussy_final.pdf},
309}
310
311
312
313%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
314%%%%% IRISA
315@InProceedings{KluterCodes08,
316  author =       {{Theo Kluter and  Philip Brisk and  Paolo Ienne and  and Edoardo Charbon}},
317  title =        {{Speculative DMA for Architecturally Visible Storage in Instruction Set Extensions}},
318  booktitle = {ISSS/CODES},
319  year =         {2008},
320}
321
322@InProceedings{KluterDAC09,
323  author =       {{Theo Kluter and  Philip Brisk and  Paolo Ienne and  and Edoardo Charbon}},
324  title =        {{Way Stealing : Cache-assisted Automatic Instruction Set Extensions}},
325  booktitle = {Design Automation Conference (DAC)},
326  year =         {2009},
327}
328
329@InProceedings{YuCodes04,
330  author =       {{Pan Yu and Tulika Mitra}},
331  title =        {{Scalable Custom Instructions Identification for Instruction Set Extensible Processors}},
332  booktitle = {ISSS/CODES},
333  year =         {2004},
334}
335
336@InProceedings{Dinh08,
337  author =       {{Quang Dinh and Deming Chen and Martin D.~F.~Wong}},
338  title =        {{Efficient ASIP Design for Configurable Processors with Fine-Grained Resource Sharing}},
339  booktitle = {ACM Internatibnal Conference Field Programmable Gate Arrays (FPGA)},
340  year =         {2008},
341}
342
343@Misc{NIOS2UG,
344  title =        {{Nios II Custom Instruction User Guide, Altera Corp.}},
345  year =         {2008},
346}
347
348%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
349%%% CITI
350@book{Polis,
351  author = {Balarin, Felice},
352  publisher = {Kluwer Academic Publishers},
353  title = {Hardware-software co-design of embedded systems : the POLIS
354        approach},
355  year = {1997}
356}
357
358@INPROCEEDINGS{Coware,
359  author = {Ivo Bolsens and Hugo J. De Man and Bill Lin and Karl Van
360                Rompaey and Steven Vercauteren and Diederik Verkest},
361  title = {Hardware/Software Co-Design of Digital Telecommunication Systems},
362  booktitle = {Proceedings of the IEEE},
363  year = {1997},
364  pages = {391--418}
365}
366
367@article{Jantsch,
368  author = {Mattias O'Nil and Axel Jantsch},
369  title = {Device Driver and DMA Controller Synthesis from HW/SW
370                        Communication protocol specifications},
371  journal = {Design Automation for Embedded Systems},
372  year = {2001},
373  volume = {6},
374  pages = {177-205}
375}
376
377@InProceedings{Park01,
378  author =   {Joonseok Park and Pedro C.~Diniz},
379  title =    {Synthesis of Pipelined Memory Access Controllers for Streamed
380                Data Applications on {FPGA}-Based Computing Engines},
381  booktitle =    {International Symposium on System Synthesis (ISSS)},
382  pages = {221-226},
383  year =     {2001},
384}
385
386@article{FR-vlsi,
387  author = {Antoine Fraboulet and Tanguy Risset},
388  title = {Master Interface for On-Chip Hardware Accelerator Burst Communications},
389  journal = {Journal of VLSI Signal Processing},
390  publisher = {Springer Science},
391  year = {2007},
392  volume = {59},
393  pages = {73-85}
394}
395
396@InProceedings{jerraya,
397  author =   {Sungjoo Yoo and Jerraya Ahmed},
398  title =    {Introduction to Hardware Abstraction Layers for SoC},
399  OPTcrossref =  {},
400  OPTkey =   {},
401  booktitle = {Design, Automation and Test in Europe Conference and Exhibition},
402  pages =    {336 -- 337},
403  year =     2003,
404  OPTeditor =    {},
405  OPTvolume =    {},
406  OPTnumber =    {},
407  OPTseries =    {},
408  OPTaddress =   {},
409  OPTmonth =     {},
410  OPTorganization = {},
411  OPTpublisher = {},
412  OPTnote =      {},
413  OPTannote =    {}
414}
415
416@INPROCEEDINGS{FAUST,
417  author = {D. Lattard and  E. Beigne and  C. Bernard and  C. Bour and  F.
418        Clermidy and  Y. Durand and  J. Durupt and  D. Varreau and  P. Vivet and
419        P. Penard and  A. Bouttier and  F. Berens}, 
420  title = "A Telecom Baseband Circuit-Based on an Asynchronous Network-on-Chip", 
421  pages = {},
422  BOOKTITLE="ISSCC\'2007", 
423  year = {2007},
424  publisher = {IEEE Computer Society},
425  address = {San Francisco, USA},
426};
427
428@inproceedings{JerrayaPetrot,
429 author = {Ahmed A. Jerraya and Aimen Bouchhima and Fr\'{e}d\'{e}ric P\'{e}trot},
430 title = {Programming models and HW-SW interfaces abstraction for multi-processor SoC},
431 booktitle = {DAC '06: Proceedings of the 43rd annual conference on Design automation},
432 year = {2006},
433 isbn = {1-59593-381-6},
434 pages = {280--285},
435 location = {San Francisco, CA, USA},
436 publisher = {ACM},
437 address = {New York, NY, USA},
438}
439
440@inproceedings{mwmr,
441 author = {E. Faure and A. Greiner and D. Genius},
442 title = {A generic hardware/software communication mechanism for
443          Multi-Processor System on Chip, Targeting Telecommunication Applications},
444 booktitle = {ReCoSoC'06},
445 year = {2006},
446 pages = {237--242},
447 address = {Montpellier, France}
448 }
449
450@inproceedings{Alberto,
451  author    = {Roberto Passerone and
452               James A. Rowson and
453               Alberto L. Sangiovanni-Vincentelli},
454  title     = {Automatic Synthesis of Interfaces Between Incompatible Protocols},
455  booktitle = {DAC},
456  year      = {1998},
457  pages     = {8-13}
458}
459
460@article{Avnit,
461  author    = {Karin Avnit and
462               Vijay D'Silva and
463               Arcot Sowmya and
464               S. Ramesh and
465               Sri Parameswaran},
466  title     = {Provably correct on-chip communication: A formal approach
467               to automatic protocol converter synthesis},
468  journal   = {ACM Trans. Design Autom. Electr. Syst.},
469  volume    = {14},
470  number    = {2},
471  year      = {2009}
472}
473
474@inproceedings{smith,
475  author    = {James Smith and
476               Giovanni De Micheli},
477  title     = {Automated Composition of Hardware Components},
478  booktitle = {DAC},
479  year      = {1998},
480  pages     = {14-19}
481}
482
483@inproceedings{Narayan,
484  author    = {Sanjiv Narayan and
485               Daniel Gajski},
486  title     = {Interfacing Incompatible Protocols Using Interface Process
487               Generation},
488  booktitle = {DAC},
489  year      = {1995},
490  pages     = {468-473}
491}
492
493@TECHREPORT{Ptolemy,
494  AUTHOR       = { E.A. Lee et al.},
495  INSTITUTION  = {University of California, Berkeley},
496  NUMBER       = {UCB/ERL No. M99/37},
497  TITLE        = {Overview of the Ptolemy Project},
498  YEAR         = {1999},
499  MONTH        = {july}
500}
501
502@article{syntol,
503    author={Paul Feautrier},
504    title={Scalable and Structured Scheduling},
505    journal={Int. J. of Parallel Programming},
506    year=2006,
507    month=May, number=5, volume=34,
508    pages="459--487"
509}
510
511@InProceedings{bee,
512  author={Christophe Alias and Fabrice Baray and Alain Darte},
513  title={Bee+Cl@k: An Implementation of Lattice-Based Array Contraction in the Source-to-Source Translator ROSE},
514  booktitle = {LCTES},
515  year = {2007},
516  publisher = {ACM}
517}
518
519%%%%%%%%%%%%% ASIP %%%%%%%%%%%%%%%%
520
521@inproceedings{DAC09,
522 author = {Kluter, Theo and Brisk, Philip and Ienne, Paolo and Charbon, Edoardo},
523 title = {Way Stealing: cache-assisted automatic instruction set extensions},
524 booktitle = {DAC '09: Proceedings of the 46th Annual Design Automation Conference},
525 year = {2009},
526 isbn = {978-1-60558-497-3},
527 pages = {31--36},
528 location = {San Francisco, California},
529 doi = {http://doi.acm.org/10.1145/1629911.1629923},
530 publisher = {ACM},
531 address = {New York, NY, USA},
532 }
533
534@inproceedings{CODES08,
535 author = {Kluter, Theo and Brisk, Philip and Ienne, Paolo and Charbon, Edoardo},
536 title = {Speculative DMA for architecturally visible storage in instruction set extensions},
537 booktitle = {CODES/ISSS '08: Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis},
538 year = {2008},
539 isbn = {978-1-60558-470-6},
540 pages = {243--248},
541 location = {Atlanta, GA, USA},
542 doi = {http://doi.acm.org/10.1145/1450135.1450191},
543 publisher = {ACM},
544 address = {New York, NY, USA},
545 }
546 
547@article{TVLSI06,
548        author = {Cong, Jason and Han, Guoling and Zhang, Zhiru},
549 title = {Architecture and compiler optimizations for data bandwidth improvement in configurable processors},
550 journal = {IEEE Trans. Very Large Scale Integr. Syst.},
551 volume = {14},
552 number = {9},
553 year = {2006},
554 issn = {1063-8210},
555 pages = {986--997},
556 doi = {http://dx.doi.org/10.1109/TVLSI.2006.884050},
557 publisher = {IEEE Educational Activities Department},
558 address = {Piscataway, NJ, USA},
559}
560
561
562@Book{NIOS2,
563  title =        {{Nios II Processor Reference Handbook}},
564  publisher =    {Altera},
565  year =         {2009},
566}
567
568
569@inproceedings{ARC08,
570 author = {Galuzzi, Carlo and Bertels, Koen},
571 title = {The Instruction-Set Extension Problem: A Survey},
572 booktitle = {ARC '08: Proceedings of the 4th international workshop on Reconfigurable Computing},
573 year = {2008},
574 isbn = {978-3-540-78609-2},
575 pages = {209--220},
576 location = {London, UK},
577 doi = {http://dx.doi.org/10.1007/978-3-540-78610-8_21},
578 publisher = {Springer-Verlag},
579 address = {Berlin, Heidelberg},
580 }
581
582@inproceedings{CODES99,
583 author = {Charot, Fran\c{c}ois and Mess\'{e}, Vincent},
584 title = {{A flexible code generation framework for the design of application specific programmable processors}},
585 booktitle = {CODES '99: Proceedings of the seventh international workshop on Hardware/software codesign},
586 year = {1999},
587 pages = {27--31},
588 location = {Rome, Italy},
589 publisher = {ACM},
590 address = {New York, NY, USA},
591 }
592
593@inproceedings{ASAP05,
594 author = {L'Hours, Ludovic},
595 title = {{Generating Efficient Custom FPGA Soft-Cores for Control-Dominated Applications}},
596 booktitle = {ASAP '05: Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors},
597 year = {2005},
598 pages = {127--133},
599 publisher = {IEEE Computer Society},
600 address = {Washington, DC, USA},
601}
602
603@inproceedings{roma,
604 author = {Menard, Daniel and Casseau, Emmanuel and Khan, Shafqat and Sentieys, Olivier and Chevobbe, St\'{e}phane and Guyetant, St\'{e}phane and David, Raphael},
605 title = {Reconfigurable Operator Based Multimedia Embedded Processor},
606 booktitle = {ARC '09: Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications},
607 year = {2009},
608 pages = {39--49},
609 location = {Karlsruhe, Germany},
610 publisher = {Springer-Verlag},
611 address = {Berlin, Heidelberg},
612 }
613
614%%%%%%%%%%%%% AUTRES %%%%%%%%%%%%%%%%
615
616@inproceedings{thales-viola,
617 author = {Viola, Jones},
618 title = {{Rapid Object Detection using a Boosted Cascade of Simple Feature}},
619 booktitle = {Proceedings of Conference on Computer Vision and Pattern recognition},
620 year = {2001},
621}
622@INPROCEEDINGS{FP:96
623        ,AUTHOR = "Paul Feautrier"
624        ,TITLE = "Automatic Parallelization in the Polytope Model"
625        ,BOOKTITLE = "The Data-Parallel Programming Model"
626        ,YEAR = 1996   
627        ,EDITOR = "Guy-Ren\'e Perrin and Alain Darte"
628        ,PAGES = "79--103"
629        ,VOLUME = "LNCS 1132"
630        ,PUBLISHER = "Springer"
631}
632
633@book{DRV:2000,
634    author={Alain Darte and Yves Robert and Fr\'ed\'eric Vivien},
635    title={Scheduling and automatic Parallelization},
636    publisher={Birkh\"auser}, year=2000
637}
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