source: anr/anr.bib @ 180

Last change on this file since 180 was 180, checked in by coach, 14 years ago

UBS
File size: 26.7 KB
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1%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
2%%%%% LIP6
3% HPC
4@InProceedings{hpc06a,
5  author    = {{M.B. Gokhale and al.}},
6  title     = {{Promises and Pitfalls of Reconfigurable Supercomputing}},
7  booktitle = {Systems and Algorithms, CSREA Press},
8  pages     = {11-20},
9  year      = {2006},
10}
11@MISC{hpc06b,
12  author =       {{D. Buell}},
13  title  =   {{Programming Reconfigurable Computers}},
14  booktitle = {Summer Institute},
15  howpublished = {http://gladiator.ncsa.uiuc.edu/PDFs/rssi06/presentations/00\_Duncan\_Buell.pdf},
16  year =         {2006},
17}
18@InProceedings{hpc07a,
19  author =       {{T. Van Court and al.}},
20  title  =   {{ Achieving High Performance with FPGA-Based Computing}},
21  booktitle = {Computer, vol. 40, no. 3},
22  pages     = {50-57},
23  month     = {mars},
24  year =         {2007},
25}
26@misc{hpc08,
27  title        = {Mitrionics},
28  howpublished = {http://www.mitrionics.com/},
29  year         = {2009},
30}
31@misc{hpc09,
32  title        = {Gidel},
33  howpublished = {http://www.gidel.com/},
34  year         = {2009},
35}
36@misc{hpc10,
37  title        = {Convey Computer},
38  howpublished = {http://www.conveycomputers.com/},
39  year         = {2009},
40}
41@InProceedings{hpc11,
42  author =      {E. El-Araby, I. Gonzalez and T. El-Ghazawi},
43  title   = {Virtual Architecture and Design Automation for Partial Reconfiguration },
44  booktitle = {HPRCTA},
45  year =         {2008},
46}
47@InProceedings{hpc12,
48  author =       {{P. Lysaght and J. Dunlop}},
49  title   = {Dynamic Reconfiguration of Field Programmable Gate Arrays},
50  booktitle = {Field Programmable Logic and Applications, Oxford, England},
51  month     = {Sept},
52  year =         {1993},
53}
54
55
56% System design
57@misc{soclib,
58  title        = {Soclib},
59  howpublished = {http://www.soclib.fr/},
60  year         = {2009},
61}
62
63@misc{system-generateur-for-dsp,
64  title        = {{System Generator for DSP}},
65  howpublished = {http://www.xilinx.com/tools/sysgen.htm},
66  year         = {2009},
67}
68
69@misc{spoc-builder,
70  title        = {{sopc builder support}},
71  howpublished = {http://www.altera.com/support/software/system/sopc/sof-sopc\_builder.html},
72  year         = {2009},
73}
74
75@InProceedings{cosy,
76    author = { J.Y Brunel, al },
77    title  = { COSY: a methodology for system design based on reusable hardware \& software IP's},
78    booktitle = { Technologies for the Information Society },
79    publisher = { IOS Press },
80    year      = {1998},
81    pages     = {709-716},
82}
83
84@InProceedings{disydent05,
85  author =       {{Ivan Aug\'{e}, Fr\'{e}d\'{e}ric P\'{e}trot, Franï¿œois Donnet and Pascal Gomez}},
86  title =        {{Platform-based design from parallel C specifications}},
87  booktitle = {IEEE Transaction on CAD of Integrated Circuits and Systems},
88  pages     = {1811--1826},
89  month     = {December},
90  year =         {2005},
91}
92@inproceedings{dspin08,
93 author = {Miro-Panades, Ivan and Clermidy, Fabien and Vivet, Pascal and Greiner, Alain},
94 title = {Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture},
95 booktitle = {NOCS '08: Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip},
96 year = {2008},
97 isbn = {978-0-7695-3098-7},
98 pages = {139--148},
99 publisher = {IEEE Computer Society},
100 address = {Washington, DC, USA},
101 }
102
103
104% HLS
105% http://mesl.ucsd.edu/spark/index.shtml
106@BOOK{spark04,
107  author     = {S. Gupta and al.},
108  title      = {SPARK: A Parallelizing Approach to the High-Level Synthesis of Digital Circuits},
109  publisher  = {Springer},
110  year       = {2004},
111}
112
113
114@INBOOK{ugh08,
115  author    = {Ivan Aug\'{e} and Fr\'{e}d\'{e}ric P\'{e}trot},
116  title     = {User Guided High Level Synthesis},
117  booktitle = {High-Level Synthesis: From Algorithm to Digital Circuits},
118  publisher = {Springer},
119  chapter   = {10},
120  year      = {2008},
121}
122
123@misc{pico,
124  title        = {{PICO}},
125  howpublished = {http://www.synfora.com/},
126  year         = {2009},
127}
128
129@misc{catapult-c,
130  title        = {{CATAPULT-C Mentor HLS tool}},
131  howpublished = {http://www.mentor.com/products/esl/high\_level\_synthesis/},
132  year         = {2009},
133}
134
135@misc{cynthetizer,
136  title        = {{Forte's CYNTHESIZER}},
137  howpublished = {http://www.forteds.com/},
138  year         = {2009},
139}
140
141
142
143%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
144%%% UBS
145
146@INBOOK{IEEEDT,
147author = {Philippe Coussy and Andres Takach},
148title = {Special Issue on High-Level Synthesis},
149journal ={IEEE Design and Test of Computers},
150volume = {25},issn = {0740-7475},
151year = {2008},
152pages = {393},doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2008.147},
153publisher = {IEEE Computer Society},
154address = {Los Alamitos, CA, USA},}
155
156
157@INBOOK{HLSBOOK,
158  author    = {P. Coussy and A. Morawiec},
159  booktitle = {High-Level Synthesis: From Algorithm to Digital Circuits},
160  publisher = {Springer},
161  year      = {2008},
162}
163
164@INBOOK{CATRENE,
165  author    = {CATRENE, Cluster for Application and Technology Research in Europe on NanotElectronics},
166  booktitle = {European Roadmap for EDA},
167  publisher = {CATRENE, Cluster for Application and Technology Research in Europe on NanotElectronics},
168  year      = {2009},
169}
170
171
172@INBOOK{IEEEDT,
173author = {Philippe Coussy and Andres Takach},
174title = {Special Issue on High-Level Synthesis},
175journal ={IEEE Design and Test of Computers},
176volume = {25},issn = {0740-7475},
177year = {2008},
178pages = {393},doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2008.147},
179publisher = {IEEE Computer Society},
180address = {Los Alamitos, CA, USA},}
181
182
183@INBOOK{HLSBOOK,
184  author    = {P. Coussy and A. Morawiec},
185  booktitle = {High-Level Synthesis: From Algorithm to Digital Circuits},
186  publisher = {Springer},
187  year      = {2008},
188}
189
190@INBOOK{CATRENE,
191  author    = {CATRENE, Cluster for Application and Technology Research in Europe on NanotElectronics},
192  booktitle = {European Roadmap for EDA},
193  publisher = {CATRENE, Cluster for Application and Technology Research in Europe on NanotElectronics},
194  year      = {2009},
195}
196
197@INBOOK{gaut08,
198  author    = {P. Coussy and al.},
199  title     = {GAUT: A High-Level Synthesis Tool for DSP applications},
200  booktitle = {High-Level Synthesis: From Algorithm to Digital Circuits},
201  publisher = {Springer},
202  year      = {2008},
203}
204
205@article{DBLP:journals/dt/CoussyT09,
206  author    = {Philippe Coussy and
207               Andres Takach},
208  title     = {Guest Editors' Introduction: Raising the Abstraction Level
209               of Hardware Design},
210  journal   = {IEEE Design {\&} Test of Computers},
211  volume    = {26},
212  number    = {4},
213  year      = {2009},
214  pages     = {4-6},
215  ee        = {http://doi.ieeecomputersociety.org/10.1109/MDT.2009.80},
216  bibsource = {DBLP, http://dblp.uni-trier.de}
217}
218
219
220@article{DBLP:journals/dt/CoussyGMT09,
221  author    = {Philippe Coussy and
222               Daniel D. Gajski and
223               Michael Meredith and
224               Andres Takach},
225  title     = {An Introduction to High-Level Synthesis},
226  journal   = {IEEE Design {\&} Test of Computers},
227  volume    = {26},
228  number    = {4},
229  year      = {2009},
230  pages     = {8-17},
231  ee        = {http://doi.ieeecomputersociety.org/10.1109/MDT.2009.69},
232  bibsource = {DBLP, http://dblp.uni-trier.de}
233}
234
235
236@article{DBLP:journals/vlsisp/ThabetCHM09,
237  author    = {Farhat Thabet and
238               Philippe Coussy and
239               Dominique Heller and
240               Eric Martin},
241  title     = {Exploration and Rapid Prototyping of DSP Applications using
242               SystemC Behavioral Simulation and High-level Synthesis},
243  journal   = {Signal Processing Systems},
244  volume    = {56},
245  number    = {2-3},
246  year      = {2009},
247  pages     = {167-186},
248  ee        = {http://dx.doi.org/10.1007/s11265-008-0235-1},
249  bibsource = {DBLP, http://dblp.uni-trier.de}
250}
251
252
253
254@inproceedings{CHAVET:2007:HAL-00153994:1,
255        title = { {A} {M}ethodology for {E}fficient {S}pace-{T}ime {A}dapter {D}esign {S}pace {E}xploration: {A} {C}ase {S}tudy of an {U}ltra {W}ide {B}and {I}nterleaver},
256        author = {{C}havet, {C}yrille and {C}oussy, {P}hilippe and {U}rard, {P}ascal and {M}artin, {E}ric},
257        abstract = {{T}his paper presents a solution to efficiently explore the design space of communication adapters. {I}n most digital signal processing ({DSP}) applications, the overall architecture of the system is significantly affected by communication architecture, so the designers need specifically optimized adapters. {B}y explicitly modeling these communications within an effective graph-theoretic model and analysis framework, we automatically generate an optimized architecture, named {S}pace-{T}ime {A}dapte{R} ({STAR}). {O}ur design flow inputs a {C} description of {I}nput/{O}utput data scheduling, and user requirements (throughput, latency, parallelism...), and formalizes communication constraints through a {R}esource {C}onstraints {G}raph ({RCG}). {T}he {RCG} properties enable an efficient architecture space exploration in order to synthesize a {STAR} component. {T}he proposed approach has been tested to design an industrial data mixing block example: an {U}ltra-{W}ideband interleaver.},
258        language = {{A}nglais},
259        affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud - {STM}icroelectronics - {STM} - {STM}icroelectronics },
260        booktitle = {{P}roceedings of the {IEEE} {I}nternational {S}ymposium on {C}ircuits and {S}ystems ({ISCAS}) {T}he {IEEE} {I}nternational {S}ymposium on {C}ircuits and {S}ystems ({ISCAS}) },
261        publisher = {{L}ibrary of {C}ongress },
262        pages = {2946 },
263        address = {{N}ew {O}rleans {\'E}tats-{U}nis d'{A}m{\'e}rique },
264        editor = {{IEEE} },
265        note = {{ISBN}:1-4244-0921-7 },
266        audience = {internationale },
267    day = {28},
268    month = {05},
269    year = {2007},
270    URL = {http://hal.archives-ouvertes.fr/hal-00153994/en/},
271    URL = {http://hal.archives-ouvertes.fr/hal-00153994/PDF/ISCAS_Chavet1992.pdf},
272}
273
274
275@inproceedings{DBLP:conf/iccad/ChavetACCJUM07,
276  author    = {Cyrille Chavet and
277               Caaliph Andriamisaina and
278               Philippe Coussy and
279               Emmanuel Casseau and
280               Emmanuel Juin and
281               Pascal Urard and
282               Eric Martin},
283  title     = {A design flow dedicated to multi-mode architectures for
284               DSP applications},
285  booktitle = {ICCAD},
286  year      = {2007},
287  pages     = {604-611},
288  ee        = {http://doi.acm.org/10.1145/1326073.1326199},
289  crossref  = {DBLP:conf/iccad/2007},
290  bibsource = {DBLP, http://dblp.uni-trier.de}
291}
292
293
294@inproceedings{DBLP:conf/glvlsi/ChavetCUM07,
295  author    = {Cyrille Chavet and
296               Philippe Coussy and
297               Pascal Urard and
298               Eric Martin},
299  title     = {A design methodology for space-time adapter},
300  booktitle = {ACM Great Lakes Symposium on VLSI},
301  year      = {2007},
302  pages     = {347-352},
303  ee        = {http://doi.acm.org/10.1145/1228784.1228868},
304  crossref  = {DBLP:conf/glvlsi/2007},
305  bibsource = {DBLP, http://dblp.uni-trier.de}
306}
307
308
309@inproceedings{CHAVET:2007:HAL-00154025:1,
310        title = { {A}pplication of a design space exploration tool to enhance interleaver generation},
311        author = {{C}havet, {C}yrille and {C}oussy, {P}hilippe and {U}rard, {P}ascal and {M}artin, {E}ric},
312        abstract = {{T}his paper presents a methodology to efficiently explore the design space of communication adapters. {I}n most digital signal processing ({DSP}) applications, the overall performance of the system is significantly affected by communication architectures, as a consequence the designers need specifically optimized adapters. {B}y explicitly modeling these communications within an effective graph-theoretic model and analysis framework, we automatically generate an optimized architecture, named {S}pace-{T}ime {A}dapte{R} ({STAR}). {O}ur design flow inputs a {C} description of {I}nput/{O}utput data scheduling, and user requirements (throughput, latency, parallelism...), and formalizes communication constraints through a {R}esource {C}onstraints {G}raph ({RCG}). {D}esign space exploration is then performed through associated tools, to synthesize a {STAR} component under time-to-market constraints. {T}he proposed approach has been tested to design an industrial data mixing block example: an {U}ltra-{W}ideband interleaver.},
313        language = {{A}nglais},
314        affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud - {STM}icroelectronics - {STM} - {STM}icroelectronics },
315        booktitle = {{P}roceedings of the {E}uropean {S}ignal {P}rocessing {C}onference ({EUSIPCO}-2007) {E}uropean {S}ignal {P}rocessing {C}onference ({EUSIPCO}-2007) },
316        publisher = {{E}urasip },
317        pages = {??? },
318        address = {{P}oznan {P}ologne },
319        audience = {internationale },
320    day = {03},
321    month = {09},
322    year = {2007},
323    URL = {http://hal.archives-ouvertes.fr/hal-00154025/en/},
324    URL = {http://hal.archives-ouvertes.fr/hal-00154025/PDF/EUSIPCO_chavet.pdf},
325}
326
327
328@inproceedings{ANDRIAMISAINA:2007:HAL-00153086:1,
329        title = { {S}ynthesis of {M}ultimode digital signal processing systems},
330        author = {{A}ndriamisaina, {C}aaliph and {C}asseau, {E}mmanuel and {C}oussy, {P}hilippe},
331        abstract = {{I}n this paper, we propose a design methodology for implementing a multimode (or multi-configuration) and multi-throughput system into a single hardware architecture. {T}he inputs of the design flow are the data flow graphs ({DFG}s), representing the different modes (i.e. the different applications to be implemented), with their respective throughput constraints. {W}hile traditional approaches merge {DFG}s together before the synthesis process, we propose to use ad-hoc scheduling and binding steps during the synthesis of each {DFG}. {T}he scheduling, which assigns operations to specific time steps, maximizes the similarity between the control steps and thus decreases the controller complexity. {T}he binding process, which assigns operations to specific functional units and data to specific storage elements, maximizes the similarity between datapaths and thus minimizes steering logic and register overhead. {F}irst results show the interest of the proposed synthesis flow.},
332        language = {{A}nglais},
333        affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud - {R}2{D}2 - {INRIA} - {IRISA} - {CNRS} : {UMR}6074 - {INRIA} - {I}nstitut {N}ational des {S}ciences {A}ppliqu{\'e}es de {R}ennes - {E}cole {N}ationale {S}up{\'e}rieure des {S}ciences {A}ppliqu{\'e}es et de {T}echnologie - {U}niversit{\'e} de {R}ennes 1 },
334        booktitle = {{P}roceeding of {A}daptive {H}ardware and {S}ystems {NASA}/{ESA} {C}onference on {A}daptive {H}ardware and {S}ystems },
335        publisher = {{AHS} },
336        pages = {7 },
337        address = {{E}dinburgh {R}oyaume-{U}ni },
338        audience = {internationale },
339    year = {2007},
340    URL = {http://hal.archives-ouvertes.fr/hal-00153086/en/},
341    URL = {http://hal.archives-ouvertes.fr/hal-00153086/PDF/PID411805.pdf},
342}
343
344
345@inproceedings{COUSSY:2005:HAL-00077301:1,
346        title = { {A} {M}ore {E}fficient and {F}lexible {DSP} {D}esign {F}low from {MATLAB}-{SIMULINK}},
347        author = {{C}oussy, {P}hilippe and {C}orre, {G}wenol{\'e} and {B}omel, {P}ierre and {S}enn, {E}ric and {M}artin, {E}ric},
348        abstract = {{T}he design of complex {D}igital {S}ignal {P}rocessing systems implies to minimize architectural cost and to maximize timing performances while taking into account communication and memory accesses constraints for the integration of dedicated hardware accelerator. {U}nfortunately, the traditional {M}atlab/{S}imulink design flows gather not very flexible hardware blocs. {I}n this paper, we present a methodology and a tool that permit the {H}igh-{L}evel {S}ynthesis of {DSP} applications, under both {I}/{O} timing and memory constraints. {B}ased on formal models and a generic architecture, this tool helps the designer in finding a reasonable trade-off between the circuit's latency and its architectural complexity. {T}he efficiency of our approach is demonstrated on the case study of a {FFT} algorithm.},
349        keywords = {{DSP} application, synthesis under memory and communication constraints},
350        language = {{A}nglais},
351        affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud },
352        booktitle = {{IEEE} {I}nternational {C}onference on {A}coustic, {S}peech and {S}ignal {P}rocessing },
353        publisher = {{IEEE} },
354        pages = {{V}ol. {V} p. 61-64 },
355        editor = {{IEEEE} },
356    year = {2005},
357    URL = {http://hal.archives-ouvertes.fr/hal-00077301/en/},
358    URL = {http://hal.archives-ouvertes.fr/hal-00077301/PDF/coussy_final.pdf},
359}
360
361
362
363%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
364%%%%% IRISA
365@InProceedings{KluterCodes08,
366  author =       {{Theo Kluter and  Philip Brisk and  Paolo Ienne and  and Edoardo Charbon}},
367  title =        {{Speculative DMA for Architecturally Visible Storage in Instruction Set Extensions}},
368  booktitle = {ISSS/CODES},
369  year =         {2008},
370}
371
372@InProceedings{KluterDAC09,
373  author =       {{Theo Kluter and  Philip Brisk and  Paolo Ienne and  and Edoardo Charbon}},
374  title =        {{Way Stealing : Cache-assisted Automatic Instruction Set Extensions}},
375  booktitle = {Design Automation Conference (DAC)},
376  year =         {2009},
377}
378
379@InProceedings{YuCodes04,
380  author =       {{Pan Yu and Tulika Mitra}},
381  title =        {{Scalable Custom Instructions Identification for Instruction Set Extensible Processors}},
382  booktitle = {ISSS/CODES},
383  year =         {2004},
384}
385
386@InProceedings{Dinh08,
387  author =       {{Quang Dinh and Deming Chen and Martin D.~F.~Wong}},
388  title =        {{Efficient ASIP Design for Configurable Processors with Fine-Grained Resource Sharing}},
389  booktitle = {ACM Internatibnal Conference Field Programmable Gate Arrays (FPGA)},
390  year =         {2008},
391}
392
393@Misc{NIOS2UG,
394  title =        {{Nios II Custom Instruction User Guide, Altera Corp.}},
395  year =         {2008},
396}
397
398%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
399%%% CITI
400@book{Polis,
401  author = {Balarin, Felice},
402  publisher = {Kluwer Academic Publishers},
403  title = {Hardware-software co-design of embedded systems : the POLIS
404        approach},
405  year = {1997}
406}
407
408@INPROCEEDINGS{Coware,
409  author = {Ivo Bolsens and Hugo J. De Man and Bill Lin and Karl Van
410                Rompaey and Steven Vercauteren and Diederik Verkest},
411  title = {Hardware/Software Co-Design of Digital Telecommunication Systems},
412  booktitle = {Proceedings of the IEEE},
413  year = {1997},
414  pages = {391--418}
415}
416
417@article{Jantsch,
418  author = {Mattias O'Nil and Axel Jantsch},
419  title = {Device Driver and DMA Controller Synthesis from HW/SW
420                        Communication protocol specifications},
421  journal = {Design Automation for Embedded Systems},
422  year = {2001},
423  volume = {6},
424  pages = {177-205}
425}
426
427@InProceedings{Park01,
428  author =   {Joonseok Park and Pedro C.~Diniz},
429  title =    {Synthesis of Pipelined Memory Access Controllers for Streamed
430                Data Applications on {FPGA}-Based Computing Engines},
431  booktitle =    {International Symposium on System Synthesis (ISSS)},
432  pages = {221-226},
433  year =     {2001},
434}
435
436@article{FR-vlsi,
437  author = {Antoine Fraboulet and Tanguy Risset},
438  title = {Master Interface for On-Chip Hardware Accelerator Burst Communications},
439  journal = {Journal of VLSI Signal Processing},
440  publisher = {Springer Science},
441  year = {2007},
442  volume = {59},
443  pages = {73-85}
444}
445
446@InProceedings{jerraya,
447  author =   {Sungjoo Yoo and Jerraya Ahmed},
448  title =    {Introduction to Hardware Abstraction Layers for SoC},
449  OPTcrossref =  {},
450  OPTkey =   {},
451  booktitle = {Design, Automation and Test in Europe Conference and Exhibition},
452  pages =    {336 -- 337},
453  year =     2003,
454  OPTeditor =    {},
455  OPTvolume =    {},
456  OPTnumber =    {},
457  OPTseries =    {},
458  OPTaddress =   {},
459  OPTmonth =     {},
460  OPTorganization = {},
461  OPTpublisher = {},
462  OPTnote =      {},
463  OPTannote =    {}
464}
465
466@INPROCEEDINGS{FAUST,
467  author = {D. Lattard and  E. Beigne and  C. Bernard and  C. Bour and  F.
468        Clermidy and  Y. Durand and  J. Durupt and  D. Varreau and  P. Vivet and
469        P. Penard and  A. Bouttier and  F. Berens}, 
470  title = "A Telecom Baseband Circuit-Based on an Asynchronous Network-on-Chip", 
471  pages = {},
472  BOOKTITLE="ISSCC\'2007", 
473  year = {2007},
474  publisher = {IEEE Computer Society},
475  address = {San Francisco, USA},
476};
477
478@inproceedings{JerrayaPetrot,
479 author = {Ahmed A. Jerraya and Aimen Bouchhima and Fr\'{e}d\'{e}ric P\'{e}trot},
480 title = {Programming models and HW-SW interfaces abstraction for multi-processor SoC},
481 booktitle = {DAC '06: Proceedings of the 43rd annual conference on Design automation},
482 year = {2006},
483 isbn = {1-59593-381-6},
484 pages = {280--285},
485 location = {San Francisco, CA, USA},
486 publisher = {ACM},
487 address = {New York, NY, USA},
488}
489
490@inproceedings{mwmr,
491 author = {E. Faure and A. Greiner and D. Genius},
492 title = {A generic hardware/software communication mechanism for
493          Multi-Processor System on Chip, Targeting Telecommunication Applications},
494 booktitle = {ReCoSoC'06},
495 year = {2006},
496 pages = {237--242},
497 address = {Montpellier, France}
498 }
499
500@inproceedings{Alberto,
501  author    = {Roberto Passerone and
502               James A. Rowson and
503               Alberto L. Sangiovanni-Vincentelli},
504  title     = {Automatic Synthesis of Interfaces Between Incompatible Protocols},
505  booktitle = {DAC},
506  year      = {1998},
507  pages     = {8-13}
508}
509
510@article{Avnit,
511  author    = {Karin Avnit and
512               Vijay D'Silva and
513               Arcot Sowmya and
514               S. Ramesh and
515               Sri Parameswaran},
516  title     = {Provably correct on-chip communication: A formal approach
517               to automatic protocol converter synthesis},
518  journal   = {ACM Trans. Design Autom. Electr. Syst.},
519  volume    = {14},
520  number    = {2},
521  year      = {2009}
522}
523
524@inproceedings{smith,
525  author    = {James Smith and
526               Giovanni De Micheli},
527  title     = {Automated Composition of Hardware Components},
528  booktitle = {DAC},
529  year      = {1998},
530  pages     = {14-19}
531}
532
533@inproceedings{Narayan,
534  author    = {Sanjiv Narayan and
535               Daniel Gajski},
536  title     = {Interfacing Incompatible Protocols Using Interface Process
537               Generation},
538  booktitle = {DAC},
539  year      = {1995},
540  pages     = {468-473}
541}
542
543@TECHREPORT{Ptolemy,
544  AUTHOR       = { E.A. Lee et al.},
545  INSTITUTION  = {University of California, Berkeley},
546  NUMBER       = {UCB/ERL No. M99/37},
547  TITLE        = {Overview of the Ptolemy Project},
548  YEAR         = {1999},
549  MONTH        = {july}
550}
551
552@article{syntol,
553    author={Paul Feautrier},
554    title={Scalable and Structured Scheduling},
555    journal={Int. J. of Parallel Programming},
556    year=2006,
557    month=May, number=5, volume=34,
558    pages="459--487"
559}
560
561@InProceedings{bee,
562  author={Christophe Alias and Fabrice Baray and Alain Darte},
563  title={Bee+Cl@k: An Implementation of Lattice-Based Array Contraction in the Source-to-Source Translator ROSE},
564  booktitle = {LCTES},
565  year = {2007},
566  publisher = {ACM}
567}
568
569%%%%%%%%%%%%% ASIP %%%%%%%%%%%%%%%%
570
571@inproceedings{DAC09,
572 author = {Kluter, Theo and Brisk, Philip and Ienne, Paolo and Charbon, Edoardo},
573 title = {Way Stealing: cache-assisted automatic instruction set extensions},
574 booktitle = {DAC '09: Proceedings of the 46th Annual Design Automation Conference},
575 year = {2009},
576 isbn = {978-1-60558-497-3},
577 pages = {31--36},
578 location = {San Francisco, California},
579 doi = {http://doi.acm.org/10.1145/1629911.1629923},
580 publisher = {ACM},
581 address = {New York, NY, USA},
582 }
583
584@inproceedings{CODES08,
585 author = {Kluter, Theo and Brisk, Philip and Ienne, Paolo and Charbon, Edoardo},
586 title = {Speculative DMA for architecturally visible storage in instruction set extensions},
587 booktitle = {CODES/ISSS '08: Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis},
588 year = {2008},
589 isbn = {978-1-60558-470-6},
590 pages = {243--248},
591 location = {Atlanta, GA, USA},
592 doi = {http://doi.acm.org/10.1145/1450135.1450191},
593 publisher = {ACM},
594 address = {New York, NY, USA},
595 }
596 
597@article{TVLSI06,
598        author = {Cong, Jason and Han, Guoling and Zhang, Zhiru},
599 title = {Architecture and compiler optimizations for data bandwidth improvement in configurable processors},
600 journal = {IEEE Trans. Very Large Scale Integr. Syst.},
601 volume = {14},
602 number = {9},
603 year = {2006},
604 issn = {1063-8210},
605 pages = {986--997},
606 doi = {http://dx.doi.org/10.1109/TVLSI.2006.884050},
607 publisher = {IEEE Educational Activities Department},
608 address = {Piscataway, NJ, USA},
609}
610
611
612@Book{NIOS2,
613  title =        {{Nios II Processor Reference Handbook}},
614  publisher =    {Altera},
615  year =         {2009},
616}
617
618
619@inproceedings{ARC08,
620 author = {Galuzzi, Carlo and Bertels, Koen},
621 title = {The Instruction-Set Extension Problem: A Survey},
622 booktitle = {ARC '08: Proceedings of the 4th international workshop on Reconfigurable Computing},
623 year = {2008},
624 isbn = {978-3-540-78609-2},
625 pages = {209--220},
626 location = {London, UK},
627 doi = {http://dx.doi.org/10.1007/978-3-540-78610-8_21},
628 publisher = {Springer-Verlag},
629 address = {Berlin, Heidelberg},
630 }
631
632@inproceedings{CODES99,
633 author = {Charot, Fran\c{c}ois and Mess\'{e}, Vincent},
634 title = {{A flexible code generation framework for the design of application specific programmable processors}},
635 booktitle = {CODES '99: Proceedings of the seventh international workshop on Hardware/software codesign},
636 year = {1999},
637 pages = {27--31},
638 location = {Rome, Italy},
639 publisher = {ACM},
640 address = {New York, NY, USA},
641 }
642
643@inproceedings{ASAP05,
644 author = {L'Hours, Ludovic},
645 title = {{Generating Efficient Custom FPGA Soft-Cores for Control-Dominated Applications}},
646 booktitle = {ASAP '05: Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors},
647 year = {2005},
648 pages = {127--133},
649 publisher = {IEEE Computer Society},
650 address = {Washington, DC, USA},
651}
652
653@inproceedings{roma,
654 author = {Menard, Daniel and Casseau, Emmanuel and Khan, Shafqat and Sentieys, Olivier and Chevobbe, St\'{e}phane and Guyetant, St\'{e}phane and David, Raphael},
655 title = {Reconfigurable Operator Based Multimedia Embedded Processor},
656 booktitle = {ARC '09: Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications},
657 year = {2009},
658 pages = {39--49},
659 location = {Karlsruhe, Germany},
660 publisher = {Springer-Verlag},
661 address = {Berlin, Heidelberg},
662 }
663
664%%%%%%%%%%%%% AUTRES %%%%%%%%%%%%%%%%
665
666@inproceedings{thales-viola,
667 author = {Viola, Jones},
668 title = {{Rapid Object Detection using a Boosted Cascade of Simple Feature}},
669 booktitle = {Proceedings of Conference on Computer Vision and Pattern recognition},
670 year = {2001},
671}
672@INPROCEEDINGS{FP:96
673        ,AUTHOR = "Paul Feautrier"
674        ,TITLE = "Automatic Parallelization in the Polytope Model"
675        ,BOOKTITLE = "The Data-Parallel Programming Model"
676        ,YEAR = 1996   
677        ,EDITOR = "Guy-Ren\'e Perrin and Alain Darte"
678        ,PAGES = "79--103"
679        ,VOLUME = "LNCS 1132"
680        ,PUBLISHER = "Springer"
681}
682
683@book{DRV:2000,
684    author={Alain Darte and Yves Robert and Fr\'ed\'eric Vivien},
685    title={Scheduling and automatic Parallelization},
686    publisher={Birkh\"auser}, year=2000
687}
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