source: anr/anr.bib @ 304

Last change on this file since 304 was 304, checked in by coach, 14 years ago

MAJ des donnees LIP6 (quasi la derniere)
File size: 31.6 KB
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1%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
2%%%%% LIP6
3% HPC
4@InProceedings{hpc06a,
5  author    = {{M.B. Gokhale and al.}},
6  title     = {{Promises and Pitfalls of Reconfigurable Supercomputing}},
7  booktitle = {Systems and Algorithms, CSREA Press},
8  pages     = {11-20},
9  year      = {2006},
10}
11@MISC{hpc06b,
12  author =       {{D. Buell}},
13  title  =   {{Programming Reconfigurable Computers}},
14  booktitle = {Summer Institute},
15  howpublished = {http://gladiator.ncsa.uiuc.edu/PDFs/rssi06/presentations/00\_Duncan\_Buell.pdf},
16  year =         {2006},
17}
18@InProceedings{hpc07a,
19  author =       {{T. Van Court and al.}},
20  title  =   {{ Achieving High Performance with FPGA-Based Computing}},
21  booktitle = {Computer, vol. 40, no. 3},
22  pages     = {50-57},
23  month     = {mars},
24  year =         {2007},
25}
26@misc{hpc08,
27  title        = {Mitrionics},
28  howpublished = {http://www.mitrionics.com/},
29  year         = {2009},
30}
31@misc{hpc09,
32  title        = {Gidel},
33  howpublished = {http://www.gidel.com/},
34  year         = {2009},
35}
36@misc{hpc10,
37  title        = {Convey Computer},
38  howpublished = {http://www.conveycomputers.com/},
39  year         = {2009},
40}
41@InProceedings{hpc11,
42  author =      {E. El-Araby, I. Gonzalez and T. El-Ghazawi},
43  title   = {Virtual Architecture and Design Automation for Partial Reconfiguration },
44  booktitle = {HPRCTA},
45  year =         {2008},
46}
47@InProceedings{hpc12,
48  author =       {{P. Lysaght and J. Dunlop}},
49  title   = {Dynamic Reconfiguration of Field Programmable Gate Arrays},
50  booktitle = {Field Programmable Logic and Applications, Oxford, England},
51  month     = {Sept},
52  year =         {1993},
53}
54
55
56% System design
57@misc{soclib,
58  title        = {Soclib},
59  howpublished = {http://www.soclib.fr/},
60  year         = {2009},
61}
62
63@misc{system-generateur-for-dsp,
64  title        = {{System Generator for DSP}},
65  howpublished = {http://www.xilinx.com/tools/sysgen.htm},
66  year         = {2009},
67}
68
69@misc{spoc-builder,
70  title        = {{sopc builder support}},
71  howpublished = {http://www.altera.com/support/software/system/sopc/sof-sopc\_builder.html},
72  year         = {2009},
73}
74
75@InProceedings{cosy,
76    author = { J.Y Brunel, al },
77    title  = { COSY: a methodology for system design based on reusable hardware \& software IP's},
78    booktitle = { Technologies for the Information Society },
79    publisher = { IOS Press },
80    year      = {1998},
81    pages     = {709-716},
82}
83
84@InProceedings{disydent05,
85  author =       {{Ivan Aug\'{e}, Fr\'{e}d\'{e}ric P\'{e}trot, Fran\c{c}ois Donnet and Pascal Gomez}},
86  title =        {{Platform-based design from parallel C specifications}},
87  booktitle = {IEEE Transaction on CAD of Integrated Circuits and Systems},
88  pages     = {1811--1826},
89  month     = {December},
90  year =         {2005},
91}
92@inproceedings{dspin08,
93 author = {Miro-Panades, Ivan and Clermidy, Fabien and Vivet, Pascal and Greiner, Alain},
94 title = {Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture},
95 booktitle = {NOCS '08: Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip},
96 year = {2008},
97 isbn = {978-0-7695-3098-7},
98 pages = {139--148},
99 publisher = {IEEE Computer Society},
100 address = {Washington, DC, USA},
101 }
102
103
104% HLS
105% http://mesl.ucsd.edu/spark/index.shtml
106@INBOOK{spark04,
107  author     = {S. Gupta and al.},
108  title      = {SPARK: A Parallelizing Approach to the High-Level Synthesis of Digital Circuits},
109  publisher  = {Springer},
110  year       = {2004},
111}
112
113
114@INBOOK{ugh08,
115  author    = {Ivan Aug\'{e} and Fr\'{e}d\'{e}ric P\'{e}trot},
116  title     = {User Guided High Level Synthesis},
117  booktitle = {High-Level Synthesis: From Algorithm to Digital Circuits},
118  publisher = {Springer},
119  year      = {2008},
120  chapter   = {10},
121  pages     = {139-148},
122}
123  %editor    = { Philippe Coussy and Adam Moriawiec},
124
125@misc{pico,
126  title        = {{PICO}},
127  howpublished = {http://www.synfora.com/},
128  year         = {2009},
129}
130
131@misc{catapult-c,
132  title        = {{CATAPULT-C Mentor HLS tool}},
133  howpublished = {http://www.mentor.com/products/esl/high\_level\_synthesis/},
134  year         = {2009},
135}
136
137@misc{cynthetizer,
138  title        = {{Forte's CYNTHESIZER}},
139  howpublished = {http://www.forteds.com/},
140  year         = {2009},
141}
142
143@inproceedings{IP-XACT-08,
144 author = {Kruijtzer, Wido and van der Wolf, Pieter and de Kock, Erwin and Stuyt, Jan and Ecker, Wolfgang and Mayer, Albrecht and Hustin, Serge and Amerijckx, Christophe and de Paoli, Serge and Vaumorin, Emmanuel},
145 title = {Industrial IP integration flows based on IP-XACT standards},
146 booktitle = {Proceedings of the conference on Design, automation and test in Europe},
147 series = {DATE '08},
148 year = {2008},
149 isbn = {978-3-9810801-3-1},
150 location = {Munich, Germany},
151 pages = {32--37},
152 numpages = {6},
153 url = {http://doi.acm.org/10.1145/1403375.1403386},
154 doi = {http://doi.acm.org/10.1145/1403375.1403386},
155 acmid = {1403386},
156 publisher = {ACM},
157 address = {New York, NY, USA},
158}
159
160
161%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
162%%% UBS
163
164@INBOOK{IEEEDT,
165author = {Philippe Coussy and Andres Takach},
166title = {Special Issue on High-Level Synthesis},
167journal ={IEEE Design and Test of Computers},
168volume = {25},issn = {0740-7475},
169year = {2008},
170pages = {393},doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2008.147},
171publisher = {IEEE Computer Society},
172address = {Los Alamitos, CA, USA},}
173
174
175@INBOOK{HLSBOOK,
176  author    = {P. Coussy and A. Morawiec},
177  booktitle = {High-Level Synthesis: From Algorithm to Digital Circuits},
178  publisher = {Springer},
179  year      = {2008},
180}
181
182@INBOOK{CATRENE,
183  author    = {CATRENE, Cluster for Application and Technology Research in Europe on NanotElectronics},
184  booktitle = {European Roadmap for EDA},
185  publisher = {CATRENE, Cluster for Application and Technology Research in Europe on NanotElectronics},
186  year      = {2009},
187}
188
189@INBOOK{gaut08,
190  author    = {P. Coussy and al.},
191  title     = {GAUT: A High-Level Synthesis Tool for DSP applications},
192  booktitle = {High-Level Synthesis: From Algorithm to Digital Circuits},
193  publisher = {Springer},
194  year      = {2008},
195}
196
197@article{DBLP:journals/dt/CoussyT09,
198  author    = {Philippe Coussy and
199               Andres Takach},
200  title     = {Guest Editors' Introduction: Raising the Abstraction Level
201               of Hardware Design},
202  journal   = {IEEE Design {\&} Test of Computers},
203  volume    = {26},
204  number    = {4},
205  year      = {2009},
206  pages     = {4-6},
207  ee        = {http://doi.ieeecomputersociety.org/10.1109/MDT.2009.80},
208  bibsource = {DBLP, http://dblp.uni-trier.de}
209}
210
211
212@article{DBLP:journals/dt/CoussyGMT09,
213  author    = {Philippe Coussy and
214               Daniel D. Gajski and
215               Michael Meredith and
216               Andres Takach},
217  title     = {An Introduction to High-Level Synthesis},
218  journal   = {IEEE Design {\&} Test of Computers},
219  volume    = {26},
220  number    = {4},
221  year      = {2009},
222  pages     = {8-17},
223  ee        = {http://doi.ieeecomputersociety.org/10.1109/MDT.2009.69},
224  bibsource = {DBLP, http://dblp.uni-trier.de}
225}
226
227
228@article{DBLP:journals/vlsisp/ThabetCHM09,
229  author    = {Farhat Thabet and
230               Philippe Coussy and
231               Dominique Heller and
232               Eric Martin},
233  title     = {Exploration and Rapid Prototyping of DSP Applications using
234               SystemC Behavioral Simulation and High-level Synthesis},
235  journal   = {Signal Processing Systems},
236  volume    = {56},
237  number    = {2-3},
238  year      = {2009},
239  pages     = {167-186},
240  ee        = {http://dx.doi.org/10.1007/s11265-008-0235-1},
241  bibsource = {DBLP, http://dblp.uni-trier.de}
242}
243
244
245
246@inproceedings{CHAVET:2007:HAL-00153994:1,
247        title = { {A} {M}ethodology for {E}fficient {S}pace-{T}ime {A}dapter {D}esign {S}pace {E}xploration: {A} {C}ase {S}tudy of an {U}ltra {W}ide {B}and {I}nterleaver},
248        author = {{C}havet, {C}yrille and {C}oussy, {P}hilippe and {U}rard, {P}ascal and {M}artin, {E}ric},
249        abstract = {{T}his paper presents a solution to efficiently explore the design space of communication adapters. {I}n most digital signal processing ({DSP}) applications, the overall architecture of the system is significantly affected by communication architecture, so the designers need specifically optimized adapters. {B}y explicitly modeling these communications within an effective graph-theoretic model and analysis framework, we automatically generate an optimized architecture, named {S}pace-{T}ime {A}dapte{R} ({STAR}). {O}ur design flow inputs a {C} description of {I}nput/{O}utput data scheduling, and user requirements (throughput, latency, parallelism...), and formalizes communication constraints through a {R}esource {C}onstraints {G}raph ({RCG}). {T}he {RCG} properties enable an efficient architecture space exploration in order to synthesize a {STAR} component. {T}he proposed approach has been tested to design an industrial data mixing block example: an {U}ltra-{W}ideband interleaver.},
250        language = {{A}nglais},
251        affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud - {STM}icroelectronics - {STM} - {STM}icroelectronics },
252        booktitle = {{P}roceedings of the {IEEE} {I}nternational {S}ymposium on {C}ircuits and {S}ystems ({ISCAS}) {T}he {IEEE} {I}nternational {S}ymposium on {C}ircuits and {S}ystems ({ISCAS}) },
253        publisher = {{L}ibrary of {C}ongress },
254        pages = {2946 },
255        address = {{N}ew {O}rleans {\'E}tats-{U}nis d'{A}m{\'e}rique },
256        editor = {{IEEE} },
257        note = {{ISBN}:1-4244-0921-7 },
258        audience = {internationale },
259    day = {28},
260    month = {05},
261    year = {2007},
262    URL = {http://hal.archives-ouvertes.fr/hal-00153994/en/},
263    URL = {http://hal.archives-ouvertes.fr/hal-00153994/PDF/ISCAS_Chavet1992.pdf},
264}
265
266
267@inproceedings{DBLP:conf/iccad/ChavetACCJUM07,
268  author    = {Cyrille Chavet and
269               Caaliph Andriamisaina and
270               Philippe Coussy and
271               Emmanuel Casseau and
272               Emmanuel Juin and
273               Pascal Urard and
274               Eric Martin},
275  title     = {A design flow dedicated to multi-mode architectures for
276               DSP applications},
277  booktitle = {ICCAD},
278  year      = {2007},
279  pages     = {604-611},
280  ee        = {http://doi.acm.org/10.1145/1326073.1326199},
281  crossref  = {DBLP:conf/iccad/2007},
282  bibsource = {DBLP, http://dblp.uni-trier.de}
283}
284
285
286@inproceedings{DBLP:conf/glvlsi/ChavetCUM07,
287  author    = {Cyrille Chavet and
288               Philippe Coussy and
289               Pascal Urard and
290               Eric Martin},
291  title     = {A design methodology for space-time adapter},
292  booktitle = {ACM Great Lakes Symposium on VLSI},
293  year      = {2007},
294  pages     = {347-352},
295  ee        = {http://doi.acm.org/10.1145/1228784.1228868},
296  crossref  = {DBLP:conf/glvlsi/2007},
297  bibsource = {DBLP, http://dblp.uni-trier.de}
298}
299
300
301@inproceedings{CHAVET:2007:HAL-00154025:1,
302        title = { {A}pplication of a design space exploration tool to enhance interleaver generation},
303        author = {{C}havet, {C}yrille and {C}oussy, {P}hilippe and {U}rard, {P}ascal and {M}artin, {E}ric},
304        abstract = {{T}his paper presents a methodology to efficiently explore the design space of communication adapters. {I}n most digital signal processing ({DSP}) applications, the overall performance of the system is significantly affected by communication architectures, as a consequence the designers need specifically optimized adapters. {B}y explicitly modeling these communications within an effective graph-theoretic model and analysis framework, we automatically generate an optimized architecture, named {S}pace-{T}ime {A}dapte{R} ({STAR}). {O}ur design flow inputs a {C} description of {I}nput/{O}utput data scheduling, and user requirements (throughput, latency, parallelism...), and formalizes communication constraints through a {R}esource {C}onstraints {G}raph ({RCG}). {D}esign space exploration is then performed through associated tools, to synthesize a {STAR} component under time-to-market constraints. {T}he proposed approach has been tested to design an industrial data mixing block example: an {U}ltra-{W}ideband interleaver.},
305        language = {{A}nglais},
306        affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud - {STM}icroelectronics - {STM} - {STM}icroelectronics },
307        booktitle = {{P}roceedings of the {E}uropean {S}ignal {P}rocessing {C}onference ({EUSIPCO}-2007) {E}uropean {S}ignal {P}rocessing {C}onference ({EUSIPCO}-2007) },
308        publisher = {{E}urasip },
309        pages = {??? },
310        address = {{P}oznan {P}ologne },
311        audience = {internationale },
312    day = {03},
313    month = {09},
314    year = {2007},
315    URL = {http://hal.archives-ouvertes.fr/hal-00154025/en/},
316    URL = {http://hal.archives-ouvertes.fr/hal-00154025/PDF/EUSIPCO_chavet.pdf},
317}
318
319
320@inproceedings{ANDRIAMISAINA:2007:HAL-00153086:1,
321        title = { {S}ynthesis of {M}ultimode digital signal processing systems},
322        author = {{A}ndriamisaina, {C}aaliph and {C}asseau, {E}mmanuel and {C}oussy, {P}hilippe},
323        abstract = {{I}n this paper, we propose a design methodology for implementing a multimode (or multi-configuration) and multi-throughput system into a single hardware architecture. {T}he inputs of the design flow are the data flow graphs ({DFG}s), representing the different modes (i.e. the different applications to be implemented), with their respective throughput constraints. {W}hile traditional approaches merge {DFG}s together before the synthesis process, we propose to use ad-hoc scheduling and binding steps during the synthesis of each {DFG}. {T}he scheduling, which assigns operations to specific time steps, maximizes the similarity between the control steps and thus decreases the controller complexity. {T}he binding process, which assigns operations to specific functional units and data to specific storage elements, maximizes the similarity between datapaths and thus minimizes steering logic and register overhead. {F}irst results show the interest of the proposed synthesis flow.},
324        language = {{A}nglais},
325        affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud - {R}2{D}2 - {INRIA} - {IRISA} - {CNRS} : {UMR}6074 - {INRIA} - {I}nstitut {N}ational des {S}ciences {A}ppliqu{\'e}es de {R}ennes - {E}cole {N}ationale {S}up{\'e}rieure des {S}ciences {A}ppliqu{\'e}es et de {T}echnologie - {U}niversit{\'e} de {R}ennes 1 },
326        booktitle = {{P}roceeding of {A}daptive {H}ardware and {S}ystems {NASA}/{ESA} {C}onference on {A}daptive {H}ardware and {S}ystems },
327        publisher = {{AHS} },
328        pages = {7 },
329        address = {{E}dinburgh {R}oyaume-{U}ni },
330        audience = {internationale },
331    year = {2007},
332    URL = {http://hal.archives-ouvertes.fr/hal-00153086/en/},
333    URL = {http://hal.archives-ouvertes.fr/hal-00153086/PDF/PID411805.pdf},
334}
335
336
337@inproceedings{COUSSY:2005:HAL-00077301:1,
338        title = { {A} {M}ore {E}fficient and {F}lexible {DSP} {D}esign {F}low from {MATLAB}-{SIMULINK}},
339        author = {{C}oussy, {P}hilippe and {C}orre, {G}wenol{\'e} and {B}omel, {P}ierre and {S}enn, {E}ric and {M}artin, {E}ric},
340        abstract = {{T}he design of complex {D}igital {S}ignal {P}rocessing systems implies to minimize architectural cost and to maximize timing performances while taking into account communication and memory accesses constraints for the integration of dedicated hardware accelerator. {U}nfortunately, the traditional {M}atlab/{S}imulink design flows gather not very flexible hardware blocs. {I}n this paper, we present a methodology and a tool that permit the {H}igh-{L}evel {S}ynthesis of {DSP} applications, under both {I}/{O} timing and memory constraints. {B}ased on formal models and a generic architecture, this tool helps the designer in finding a reasonable trade-off between the circuit's latency and its architectural complexity. {T}he efficiency of our approach is demonstrated on the case study of a {FFT} algorithm.},
341        keywords = {{DSP} application, synthesis under memory and communication constraints},
342        language = {{A}nglais},
343        affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud },
344        booktitle = {{IEEE} {I}nternational {C}onference on {A}coustic, {S}peech and {S}ignal {P}rocessing },
345        publisher = {{IEEE} },
346        pages = {{V}ol. {V} p. 61-64 },
347        editor = {{IEEEE} },
348    year = {2005},
349    URL = {http://hal.archives-ouvertes.fr/hal-00077301/en/},
350    URL = {http://hal.archives-ouvertes.fr/hal-00077301/PDF/coussy_final.pdf},
351}
352
353
354
355%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
356%%%%% IRISA
357@InProceedings{KluterCodes08,
358  author =       {{Theo Kluter and  Philip Brisk and  Paolo Ienne and  and Edoardo Charbon}},
359  title =        {{Speculative DMA for Architecturally Visible Storage in Instruction Set Extensions}},
360  booktitle = {ISSS/CODES},
361  year =         {2008},
362}
363
364@InProceedings{KluterDAC09,
365  author =       {{Theo Kluter and  Philip Brisk and  Paolo Ienne and  and Edoardo Charbon}},
366  title =        {{Way Stealing : Cache-assisted Automatic Instruction Set Extensions}},
367  booktitle = {Design Automation Conference (DAC)},
368  year =         {2009},
369}
370
371@InProceedings{YuCodes04,
372  author =       {{Pan Yu and Tulika Mitra}},
373  title =        {{Scalable Custom Instructions Identification for Instruction Set Extensible Processors}},
374  booktitle = {ISSS/CODES},
375  year =         {2004},
376}
377
378@InProceedings{Dinh08,
379  author =       {{Quang Dinh and Deming Chen and Martin D.~F.~Wong}},
380  title =        {{Efficient ASIP Design for Configurable Processors with Fine-Grained Resource Sharing}},
381  booktitle = {ACM Internatibnal Conference Field Programmable Gate Arrays (FPGA)},
382  year =         {2008},
383}
384
385@Misc{NIOS2UG,
386  title =        {{Nios II Custom Instruction User Guide, Altera Corp.}},
387  year =         {2008},
388}
389
390%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
391%%% CITI
392@book{Polis,
393  author = {Balarin, Felice},
394  publisher = {Kluwer Academic Publishers},
395  title = {Hardware-software co-design of embedded systems : the POLIS
396        approach},
397  year = {1997}
398}
399
400@INPROCEEDINGS{Coware,
401  author = {Ivo Bolsens and Hugo J. De Man and Bill Lin and Karl Van
402                Rompaey and Steven Vercauteren and Diederik Verkest},
403  title = {Hardware/Software Co-Design of Digital Telecommunication Systems},
404  booktitle = {Proceedings of the IEEE},
405  year = {1997},
406  pages = {391--418}
407}
408
409@article{Jantsch,
410  author = {Mattias O'Nil and Axel Jantsch},
411  title = {Device Driver and DMA Controller Synthesis from HW/SW
412                        Communication protocol specifications},
413  journal = {Design Automation for Embedded Systems},
414  year = {2001},
415  volume = {6},
416  pages = {177-205}
417}
418
419@InProceedings{Park01,
420  author =   {Joonseok Park and Pedro C.~Diniz},
421  title =    {Synthesis of Pipelined Memory Access Controllers for Streamed
422                Data Applications on {FPGA}-Based Computing Engines},
423  booktitle =    {International Symposium on System Synthesis (ISSS)},
424  pages = {221-226},
425  year =     {2001},
426}
427
428@article{FR-vlsi,
429  author = {Antoine Fraboulet and Tanguy Risset},
430  title = {Master Interface for On-Chip Hardware Accelerator Burst Communications},
431  journal = {Journal of VLSI Signal Processing},
432  publisher = {Springer Science},
433  year = {2007},
434  volume = {59},
435  pages = {73-85}
436}
437
438@InProceedings{jerraya,
439  author =   {Sungjoo Yoo and Jerraya Ahmed},
440  title =    {Introduction to Hardware Abstraction Layers for SoC},
441  OPTcrossref =  {},
442  OPTkey =   {},
443  booktitle = {Design, Automation and Test in Europe Conference and Exhibition},
444  pages =    {336 -- 337},
445  year =     2003,
446  OPTeditor =    {},
447  OPTvolume =    {},
448  OPTnumber =    {},
449  OPTseries =    {},
450  OPTaddress =   {},
451  OPTmonth =     {},
452  OPTorganization = {},
453  OPTpublisher = {},
454  OPTnote =      {},
455  OPTannote =    {}
456}
457
458@INPROCEEDINGS{FAUST,
459  author = {D. Lattard and  E. Beigne and  C. Bernard and  C. Bour and  F.
460        Clermidy and  Y. Durand and  J. Durupt and  D. Varreau and  P. Vivet and
461        P. Penard and  A. Bouttier and  F. Berens}, 
462  title = "A Telecom Baseband Circuit-Based on an Asynchronous Network-on-Chip", 
463  pages = {},
464  BOOKTITLE="ISSCC\'2007", 
465  year = {2007},
466  publisher = {IEEE Computer Society},
467  address = {San Francisco, USA},
468};
469
470@inproceedings{JerrayaPetrot,
471 author = {Ahmed A. Jerraya and Aimen Bouchhima and Fr\'{e}d\'{e}ric P\'{e}trot},
472 title = {Programming models and HW-SW interfaces abstraction for multi-processor SoC},
473 booktitle = {DAC '06: Proceedings of the 43rd annual conference on Design automation},
474 year = {2006},
475 isbn = {1-59593-381-6},
476 pages = {280--285},
477 location = {San Francisco, CA, USA},
478 publisher = {ACM},
479 address = {New York, NY, USA},
480}
481
482@inproceedings{mwmr,
483 author = {E. Faure and A. Greiner and D. Genius},
484 title = {A generic hardware/software communication mechanism for
485          Multi-Processor System on Chip, Targeting Telecommunication Applications},
486 booktitle = {ReCoSoC'06},
487 year = {2006},
488 pages = {237--242},
489 address = {Montpellier, France}
490 }
491
492@inproceedings{Alberto,
493  author    = {Roberto Passerone and
494               James A. Rowson and
495               Alberto L. Sangiovanni-Vincentelli},
496  title     = {Automatic Synthesis of Interfaces Between Incompatible Protocols},
497  booktitle = {DAC},
498  year      = {1998},
499  pages     = {8-13}
500}
501
502@article{Avnit,
503  author    = {Karin Avnit and
504               Vijay D'Silva and
505               Arcot Sowmya and
506               S. Ramesh and
507               Sri Parameswaran},
508  title     = {Provably correct on-chip communication: A formal approach
509               to automatic protocol converter synthesis},
510  journal   = {ACM Trans. Design Autom. Electr. Syst.},
511  volume    = {14},
512  number    = {2},
513  year      = {2009}
514}
515
516@inproceedings{smith,
517  author    = {James Smith and
518               Giovanni De Micheli},
519  title     = {Automated Composition of Hardware Components},
520  booktitle = {DAC},
521  year      = {1998},
522  pages     = {14-19}
523}
524
525@inproceedings{Narayan,
526  author    = {Sanjiv Narayan and
527               Daniel Gajski},
528  title     = {Interfacing Incompatible Protocols Using Interface Process
529               Generation},
530  booktitle = {DAC},
531  year      = {1995},
532  pages     = {468-473}
533}
534
535@TECHREPORT{Ptolemy,
536  AUTHOR       = { E.A. Lee et al.},
537  INSTITUTION  = {University of California, Berkeley},
538  NUMBER       = {UCB/ERL No. M99/37},
539  TITLE        = {Overview of the Ptolemy Project},
540  YEAR         = {1999},
541  MONTH        = {july}
542}
543
544@article{syntol,
545    author={Paul Feautrier},
546    title={Scalable and Structured Scheduling},
547    journal={Int. J. of Parallel Programming},
548    year=2006,
549    month=May, number=5, volume=34,
550    pages="459--487"
551}
552
553@InProceedings{bee,
554  author={Christophe Alias and Fabrice Baray and Alain Darte},
555  title={Bee+Cl@k: An Implementation of Lattice-Based Array Contraction in the Source-to-Source Translator ROSE},
556  booktitle = {LCTES},
557  year = {2007},
558  publisher = {ACM}
559}
560
561%%%%%%%%%%%%% ASIP %%%%%%%%%%%%%%%%
562
563@inproceedings{DAC09,
564 author = {Kluter, Theo and Brisk, Philip and Ienne, Paolo and Charbon, Edoardo},
565 title = {Way Stealing: cache-assisted automatic instruction set extensions},
566 booktitle = {DAC '09: Proceedings of the 46th Annual Design Automation Conference},
567 year = {2009},
568 isbn = {978-1-60558-497-3},
569 pages = {31--36},
570 location = {San Francisco, California},
571 doi = {http://doi.acm.org/10.1145/1629911.1629923},
572 publisher = {ACM},
573 address = {New York, NY, USA},
574 }
575
576@inproceedings{CODES08,
577 author = {Kluter, Theo and Brisk, Philip and Ienne, Paolo and Charbon, Edoardo},
578 title = {Speculative DMA for architecturally visible storage in instruction set extensions},
579 booktitle = {CODES/ISSS '08: Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis},
580 year = {2008},
581 isbn = {978-1-60558-470-6},
582 pages = {243--248},
583 location = {Atlanta, GA, USA},
584 doi = {http://doi.acm.org/10.1145/1450135.1450191},
585 publisher = {ACM},
586 address = {New York, NY, USA},
587 }
588 
589@article{TVLSI06,
590        author = {Cong, Jason and Han, Guoling and Zhang, Zhiru},
591 title = {Architecture and compiler optimizations for data bandwidth improvement in configurable processors},
592 journal = {IEEE Trans. Very Large Scale Integr. Syst.},
593 volume = {14},
594 number = {9},
595 year = {2006},
596 issn = {1063-8210},
597 pages = {986--997},
598 doi = {http://dx.doi.org/10.1109/TVLSI.2006.884050},
599 publisher = {IEEE Educational Activities Department},
600 address = {Piscataway, NJ, USA},
601}
602
603
604@Book{NIOS2,
605  title =        {{Nios II Processor Reference Handbook}},
606  publisher =    {Altera},
607  year =         {2009},
608}
609
610
611@inproceedings{ARC08,
612 author = {Galuzzi, Carlo and Bertels, Koen},
613 title = {The Instruction-Set Extension Problem: A Survey},
614 booktitle = {ARC '08: Proceedings of the 4th international workshop on Reconfigurable Computing},
615 year = {2008},
616 isbn = {978-3-540-78609-2},
617 pages = {209--220},
618 location = {London, UK},
619 doi = {http://dx.doi.org/10.1007/978-3-540-78610-8_21},
620 publisher = {Springer-Verlag},
621 address = {Berlin, Heidelberg},
622 }
623
624@inproceedings{CODES99,
625 author = {Charot, Fran\c{c}ois and Mess\'{e}, Vincent},
626 title = {{A flexible code generation framework for the design of application specific programmable processors}},
627 booktitle = {CODES '99: Proceedings of the seventh international workshop on Hardware/software codesign},
628 year = {1999},
629 pages = {27--31},
630 location = {Rome, Italy},
631 publisher = {ACM},
632 address = {New York, NY, USA},
633 }
634
635@inproceedings{ASAP05,
636 author = {L'Hours, Ludovic},
637 title = {{Generating Efficient Custom FPGA Soft-Cores for Control-Dominated Applications}},
638 booktitle = {ASAP '05: Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors},
639 year = {2005},
640 pages = {127--133},
641 publisher = {IEEE Computer Society},
642 address = {Washington, DC, USA},
643}
644
645@inproceedings{roma,
646 author = {Menard, Daniel and Casseau, Emmanuel and Khan, Shafqat and Sentieys, Olivier and Chevobbe, St\'{e}phane and Guyetant, St\'{e}phane and David, Raphael},
647 title = {Reconfigurable Operator Based Multimedia Embedded Processor},
648 booktitle = {ARC '09: Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications},
649 year = {2009},
650 pages = {39--49},
651 location = {Karlsruhe, Germany},
652 publisher = {Springer-Verlag},
653 address = {Berlin, Heidelberg},
654 }
655
656%%%%%%%%%%%%% AUTRES %%%%%%%%%%%%%%%%
657
658@inproceedings{thales-viola,
659 author = {Viola, Jones},
660 title = {{Rapid Object Detection using a Boosted Cascade of Simple Feature}},
661 booktitle = {Proceedings of Conference on Computer Vision and Pattern recognition},
662 year = {2001},
663}
664@INPROCEEDINGS{FP:96
665        ,AUTHOR = "Paul Feautrier"
666        ,TITLE = "Automatic Parallelization in the Polytope Model"
667        ,BOOKTITLE = "The Data-Parallel Programming Model"
668        ,YEAR = 1996   
669        ,EDITOR = "Guy-Ren\'e Perrin and Alain Darte"
670        ,PAGES = "79--103"
671        ,VOLUME = "LNCS 1132"
672        ,PUBLISHER = "Springer"
673}
674
675@book{DRV:2000,
676    author={Alain Darte and Yves Robert and Fr\'ed\'eric Vivien},
677    title={Scheduling and automatic Parallelization},
678    publisher={Birkh\"auser}, year=2000
679}
680
681@Article{Feau:92aa,
682  author =       "Paul Feautrier",
683  title =        "Some Efficient Solutions to the Affine Scheduling
684                 Problem, {I}, One Dimensional Time",
685  volume =       "21",
686  number =       "5",
687  month =        Oct,
688  pages =        "313--348",
689  journal =      "Int. J. of Parallel Programming",
690  year =         "1992"
691}
692
693@Article{Feau:92bb,
694  author =       "Paul Feautrier",
695  title =        "Some Efficient Solutions to the Affine Scheduling
696                 Problem, {II}, Multidimensional Time",
697  volume =       "21",
698  number =       "6",
699  journal =      "Int. J. of Parallel Programming",
700  month =        Dec,
701  pages =        "389--420",
702  year =         "1992"
703}
704
705@ARTICLE{Feau:96
706        ,AUTHOR = {Paul Feautrier}
707        ,TITLE = {Distribution Automatique des Donn\'es et des
708         calculs} 
709        ,JOURNAL = {T.S.I.}
710        ,YEAR = 1996, VOLUME = 15, NUMBER = 5, PAGES = {529--557}
711}
712
713%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
714%%% IA
715
716@PHDTHESIS{ia-hdr-phd,
717  author    = {Ivan Aug\'{e}},
718  title     = {Th\`ese d'Habilitation \`a Diriger des Recherches:
719               Synth\`ese de haut niveau \& Int\'egration
720               des syst\`emes mat\'eriel/logiciel},
721  school    = {Universit\'e Pierre et Marie Curie},
722  year      = {2009},
723  month     = {12},
724}
725
726@MISC{ia-hdr,
727  author    = {Ivan Aug\'{e}},
728  title     = {Th\`ese d'Habilitation \`a Diriger des Recherches:
729               Synth\`ese de haut niveau \& Int\'egration
730               des syst\`emes mat\'eriel/logiciel},
731  howpublished = {Universit\'e Pierre et Marie Curie},
732  year      = {2009},
733  month     = {12},
734}
735
736@INBOOK{ia-ugh08,
737  author    = {Ivan Aug\'{e} and Fr\'{e}d\'{e}ric P\'{e}trot},
738  title     = {User Guided High Level Synthesis},
739  booktitle = {High-Level Synthesis: From Algorithm to Digital Circuits},
740  publisher = {Springer},
741  chapter   = {10},
742  year      = {2008},
743  pages     = {139-148},
744}
745  %editor    = {Philippe Coussy and Adam Moriawiec},
746
747@misc{ia-ugh-09-aspdac,
748  author   = {Fr\'ed\'eric P\'etrot and Ivan Aug\'e},
749  title    = {User Guided High Level Synthesis},
750  booktitle= {Workshop "High-Level Synthesis: Next Step to Efficient ESL Design",
751                      in conjunction with ASP-DAC},
752  year     = {2009},
753}
754
755@misc{ia-ugh-08-date,
756  author =  {Fr\'ed\'eric P\'etrot and Ivan Aug\'e},
757  title = {User Guided High Level Synthesis},
758  booktitle= { Workshop "The New Wave of the High-Level Synthesis",
759                      in conjunction with DATE},
760  year       = {2008},
761}
762
763%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
764%%% AG
765
766@article{ag-1,
767    author = {Zhen Zhang and Alain Greiner and Mounir Benabdenbi},
768    title = {Fully distributed initialization procedure for a 2D-Mesh NoC, including off-line BIST and partial deactivation of faulty components},
769    journal ={On-Line Testing Symposium, IEEE International},
770    volume = {0},
771    isbn = {978-1-4244-7724-1},
772    year = {2010},
773    pages = {194-196},
774    doi = {http://doi.ieeecomputersociety.org/10.1109/IOLTS.2010.5560209},
775    publisher = {IEEE Computer Society},
776    address = {Los Alamitos, CA, USA},
777}
778
779@inproceedings{ag-2,
780    author    = {Greiner Alain and Faure Etienne and Pouillon Nicolas and Genius Dani\'ela},
781    title     = {A Generic Hardware/Software Communication Middleware for
782                 Streaming Applications on Shared Memory Multi Processor Systems-on-Chip},
783    booktitle = {Forum on Specification \& Design Languages (FDL 2009)},
784    isbn      = { 978-2-9530504-1-7},
785    month     = {September},
786    year      = {2009},
787    address   = {Nice, France},
788}
789
790@inproceedings{ag-3,
791    author    = {Porquet, Jo\"{e}l and Schwarz, Christian and Greiner, Alain},
792    title     = {Multi-compartment: A new architecture for secure
793                 co-hosting on SoC },
794    booktitle = {Proceedings of the 11th international conference on System-on-chip},
795    series    = {SOC'09},
796    month     = {October},
797    year      = {2009},
798    isbn      = {978-1-4244-4466-3},
799    location  = {Tampere, Finland},
800    pages     = {124-127},
801    numpages  = {4},
802    url       = {http://portal.acm.org/citation.cfm?id=1736530.1736555},
803    publisher = {IEEE Press},
804    address   = {Piscataway, NJ, USA},
805}
806
807@inproceedings{ag-4,
808    author    = {Miro-Panades, Ivan and Clermidy, Fabien and Vivet, Pascal and Greiner, Alain},
809    title     = {Physical Implementation of the DSPIN Network-on-Chip in the
810                 FAUST Architecture},
811    booktitle = {Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip},
812    series    = {NOCS'08},
813    year      = {2008},
814    month     = {April},
815    isbn      = {978-0-7695-3098-7},
816    location  = {Newcastle, UK},
817    pages     = {139-148},
818    numpages = {10},
819    url = {http://portal.acm.org/citation.cfm?id=1397757.1397994},
820    publisher = {IEEE Computer Society},
821    address   = {Washington, DC, USA},
822}
823
824
825
826%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
827%%% XXXX
828
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