[16] | 1 | % les objectifs globaux, |
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[21] | 2 | A digital system is an application integrated into one or several chips. |
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| 3 | These chips can be embedded in devices such as a personal digital assistant |
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| 4 | (PDA), ambiant computing component, wireless sensor network (WSN). They can |
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| 5 | also be used on a board connected to a PC to accelerate an application like |
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| 6 | in High-Performance Computing (HPC) and in High-Speed Signal Processing (HSSP). |
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| 7 | Digital system design has been investigated since eighties by using Applications |
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| 8 | Specific Integrated Circuits (ASIC), Digital Signal Processing (DSP) and parallel computing on |
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| 9 | multiprocessor machines or networks. More recently, since the end of nineties, |
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| 10 | other technologies appeared like Very Large Instruction Word (VLIW), Application |
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| 11 | Specific Instruction Processors (ASIP), System on Chip (SoC), Multi-Processors |
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| 12 | SoC (MPSoC). |
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[16] | 13 | \\ |
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[21] | 14 | During these last decades, digital systems are more and more reserved |
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| 15 | to major companies targeting high volume market due to the design and fabrication |
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| 16 | costs of ASIC technologies due to increasing NRE (Non Recurring-Engineering) charges. |
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[16] | 17 | Nowadays Field Programmable Gate Arrays (FPGA), like Virtex5 from Xilinx |
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[21] | 18 | and Stratix4 from Altera, can implement a complete SoC with multiple processors and |
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| 19 | several coprocessors for less than 10K euros per device. |
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| 20 | In addition, Electronic System Level (ESL) design methodologies (Virtual Prototyping, |
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| 21 | Co-design, High-Level Synthesis...) become mature and allow to |
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[16] | 22 | automate design and to drastically decrease its cost in terms of man power. |
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[21] | 23 | Thus, coupling both FPGA and ESL methodologies will soon allow small and medium |
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| 24 | enterprises (SMEs) to get into new and low-volume markets, to design highly innovative devices, |
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| 25 | to prototype complete complex embedded systems, to realize HPC or HSSP applications. |
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[16] | 26 | \par |
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[21] | 27 | The objective of COACH is to provide an environment to design emmbedded systems and |
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| 28 | HPC applications on FPGA devices. The COACH framework will allow designer to explore various |
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| 29 | software/hardware partitioning scenario of the target application through timing and functional |
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[16] | 30 | simulations and to generate automatically both the software and the |
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[21] | 31 | synthesizable description of the hardware. Exploration and design are mainly |
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| 32 | driven by throughput, latency and/or power consumption criteria. |
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| 33 | The main contributions of the project are: |
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[16] | 34 | \begin{itemize} |
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[21] | 35 | \item Targeted hardware architecture and technology: |
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| 36 | COACH will handle both Altera and Xilinx FPGA technologies. COACH will define |
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| 37 | architectural templates that can be customized by additional dedicated coprocessors and ASIPs. |
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| 38 | The parameters of the architectural templates will be the number of CPU, the operating system... |
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| 39 | %the coprocessors, the number and the size of the FIFO communication channels |
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| 40 | Basically, the 3 following architectural templates will be provided: |
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| 41 | A COACH architectural template based on the MIPS of the TSAR ANR project and a VCI ring bus, |
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| 42 | An Altera architectural template based on the NIOS and the AVALON bus, |
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| 43 | %FIXME |
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| 44 | % The following point has to be confirmed by XILINX |
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| 45 | % Microblaze+OPB => ARM+Amba ??? |
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| 46 | A Xilinx architectural template based on the MICROBLAZE and the OPB bus. |
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| 47 | Moreover, the specification of the application will be independant of both the template |
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| 48 | architecture and the selected technology. |
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| 49 | \item Design space exploration: The COACH environment will allow to select and parametrize |
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| 50 | the target architecture, to define hardware/software partitioning and to profile the application. |
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| 51 | For each point of design space exploration, metrics such as throughput, latency, power consumption, |
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| 52 | area, memory allocation and data locality will be provided. |
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| 53 | This criteria will be evaluated by using virtual prototyping and high-level estimation methodologies. |
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| 54 | \item Hardware accelerators synthesis (HAS): COACH will allow to generate automatically hardware accelerators |
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| 55 | when required. Hence, High-Level Synthesis (HLS) tools, ASIP design environement and |
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| 56 | source-level transformations (loop transformations and memory optimisation) will be provided. |
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| 57 | This will allow to further explore the micro-architectural design space. |
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[16] | 58 | \end{itemize} |
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[21] | 59 | %In HPC, the kind of targeted application is an existing one running on PC. |
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| 60 | %COACH helps designer to accelerate it by migrating critical parts into a |
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| 61 | %SoC implemented on a FPGA plugged to the PC bus.\\ |
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| 62 | %FIXME licence a speficier |
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| 63 | The COACH environment will be designed to abstract the hardware as much as possible to the end user. |
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| 64 | It will thus be mainly dedicated to system designers. |
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| 65 | Finally COACH will be developped under the General Public Licence for the software tools. |
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| 66 | and USAGE LIBRE NON COMMERCIAL for the COACH arhitecture. |
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| 67 | %The COACH architectural templates will be freely distributed. |
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[16] | 68 | % |
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| 69 | % verrous scientifiques et techniques |
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| 70 | \mbox{}\vspace*{.9ex}\par |
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[21] | 71 | System design is a very complex task this project will simplify as much as possible. |
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| 72 | For this purpose the following scientific and technological barriers will be addressed: |
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[16] | 73 | \begin{itemize} |
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[21] | 74 | \item The clock frequency of the coprocessors generated by the HLS must respect |
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| 75 | the frequency of the processors and the system bus. |
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| 76 | \item HLS tools are sensitive to the coding style of the input specification |
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| 77 | and the domain they target (control vs. data dominated). The HLS tools of COACH must have a |
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| 78 | common language and coding style to avoid engineering work to the designer. |
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| 79 | \item The main problem in HPC comes from timing performance and implementation of the communication |
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| 80 | between the PC and the FPGA. |
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| 81 | %FIXME: a completer loop tranfrom?, ASIP?, ... |
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[16] | 82 | \end{itemize} |
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| 83 | % |
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| 84 | % le programme de travail |
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| 85 | \vspace*{.9ex}\par |
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| 86 | COACH is the result of the will of several laboratories to unify their know |
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| 87 | hows and skills in the following domains: Operating system and hardware |
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[21] | 88 | communication (TIMA and CITI), SoC and MPSoC (LIP6 and TIMA), ASIP (IRISA) and |
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| 89 | HLS (LIP6 and Lab-STICC) and loop tranformations (LIP). |
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| 90 | COACH does not start from scratch but relies |
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| 91 | on the SocLib platform~\cite{soclib} with the MUTEX and DNA/OS operating system for |
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| 92 | SoC and MPSoC prototyping, on GAUT~\cite{gaut08} and UGH~\cite{ugh08} for HLS, on |
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| 93 | ROMA~\cite{roma} for ASIP, on SYNTOL~\cite{syntol} and BEE~\cite{bee} for loop tranformations. |
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| 94 | The project objective is to enhance and seamlessly integrate these tools into |
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| 95 | a unique open source framework. |
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| 96 | %masking these domains and its different tools to the system designer. |
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| 97 | The main steps of this project are: |
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| 98 | 1) Definition of the user inputs: application description as set of communicating tasks, each |
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| 99 | task beeing described in C++ language; architectural template with its parameters; design constraints. |
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| 100 | 2) Definition of the internal \xcoach format for representing a task. |
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| 101 | 3) Development of a GCC pluggin for generating the \xcoach representation of a C++ task. |
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| 102 | 4) Adaptation of the existing HLS tools to read and write the \xcoach format. This will allow to |
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| 103 | swap from one tool to an other one and to chain them. |
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| 104 | 5) Modification of the Design System eXplorator DSX of the SocLib platform to let the user |
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| 105 | explore the design space and then to generate the bitstream. |
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| 106 | %FIXME : a completer |
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[16] | 107 | \par |
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[21] | 108 | The role of the industrial partners BULL, THALES, XXX is to provide real |
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| 109 | benchmarks to guide the design of the framework and to prove that COACH is |
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[16] | 110 | usuable and cover a large spectrum of applications. |
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| 111 | % |
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| 112 | % les retombées scientifiques, techniques et économiques |
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| 113 | \vspace*{.9ex}\par |
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[21] | 114 | The main scientific contributions of the project are: |
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| 115 | to make high-level synthesis an elementary tool of system design, |
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| 116 | to unify various synthesis techniques (same input and output formats) |
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[16] | 117 | allowing the designer to swap from one to an other and even to chain them |
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| 118 | without rewritting effort, |
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[21] | 119 | to provide a system description independent of the target architecture and |
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| 120 | the FPGA family. |
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[16] | 121 | \par |
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| 122 | The market of embedded system and HPC is about 4,600 M\$ today and is |
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| 123 | estimated to 5,600 M\$ in 2012. |
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| 124 | This market is dominated by Multi-core CPUs based solution and is controlled |
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| 125 | by major companies that can support the very high Non Recurring Engineering (NRE) |
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| 126 | costs involved in designing such system. |
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[21] | 127 | Small and medium companies can only be present in this market with GPUs based solutions that have |
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[16] | 128 | low NRE costs but limit the application domains.\\ |
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| 129 | COACH reduces the NRE costs to the design costs (the FPGA device being only a few |
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| 130 | K\euro) and reduces drastically them. |
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| 131 | So one can expect that tools targeting FPGA and dedicated to software developpers |
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| 132 | will gain market share over Multi-core CPUs and GPUs HPC based solutions. |
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| 133 | Moreover this market can also be boosted by small and even very small new companies |
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| 134 | that will be able to propose embedded system and accelerating solutions for standard |
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| 135 | software applications with acceptable prices.\\ |
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[21] | 136 | The two major FPGA companies Altera and Xilinx expect this by supporting |
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[16] | 137 | and participating in this project. |
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| 138 | |
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