Changeset 21 for anr/section-1.tex


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Dec 31, 2009, 8:27:21 AM (15 years ago)
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coach
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    r16 r21  
    11% les objectifs globaux,
    2 An embedded system is an application integrated into one or several chips
    3 in order to accelerate it or to embedd it into a small device such as a
    4 personal digital assistant (PDA). This topic is investigated since 80s
    5 using Applications Specific Integrated Circuits (ASIC), Digital Signal
    6 Processing (DSP) and parallel computing on multiprocessor machines or
    7 networks.  More recently, since end of 90s, other technologies appeared
    8 like Very Large Instruction Word (VLIW), Application Specific Instruction
    9 Processors (ASIP), System on Chip (SoC), Multi-Processors SoC (MPSoC).
     2A digital system is an application integrated into one or several chips.
     3These chips can be embedded in devices such as a personal digital assistant
     4(PDA), ambiant computing component, wireless sensor network (WSN). They can
     5also be used on a board connected to a PC to accelerate an application like
     6in High-Performance Computing (HPC) and in High-Speed Signal Processing (HSSP).
     7Digital system design has  been investigated since eighties by using Applications
     8Specific Integrated Circuits (ASIC), Digital Signal Processing (DSP) and parallel computing on
     9multiprocessor machines or networks.  More recently, since the end of nineties,
     10other technologies appeared like Very Large Instruction Word (VLIW), Application
     11Specific Instruction Processors (ASIP), System on Chip (SoC), Multi-Processors
     12SoC (MPSoC).
    1013\\
    11 During these last decades embedded system was reserved to major industrial
    12 companies targeting high volume market due to the design and fabrication
    13 costs.
     14During these last decades, digital systems are more and more reserved
     15to major companies targeting high volume market due to the design and fabrication
     16costs of ASIC technologies due to increasing NRE (Non Recurring-Engineering) charges.
    1417Nowadays Field Programmable Gate Arrays (FPGA), like Virtex5 from Xilinx
    15 and Stratix4 from Altera, can implement a SoC with multiple processors and
    16 several coprocessors for less than 10K euros per item.
    17 In addition, High Level Synthesis (HLS) becomes more mature and allows to
     18and Stratix4 from Altera, can implement a complete SoC with multiple processors and
     19several coprocessors for less than 10K euros per device.
     20In addition, Electronic System Level (ESL) design methodologies (Virtual Prototyping,
     21Co-design, High-Level Synthesis...) become mature and allow to
    1822automate design and to drastically decrease its cost in terms of man power.
    19 Thus, both FPGA and HLS tend to spread over HPC for small companies
    20 targeting low volume markets.
     23Thus, coupling both FPGA and ESL methodologies will soon allow small and medium
     24enterprises (SMEs) to get into new and low-volume markets, to design highly innovative devices,
     25to prototype complete complex embedded systems, to realize HPC or HSSP applications.
    2126\par
    22 To get an efficient embedded system, designer has to take into account
    23 application characteristics when it chooses one of the former technologies.
    24 This choice is not easy and in most cases designer has to try different
    25 technologies to retain the most adapted one.
    26 \\
    27 The first objective of COACH is to provide a framework to
    28 design embedded system on FPGA device.
    29 COACH framework allows designer to explore various software/hardware
    30 partitions of the target application, to run timing and functional
     27The objective of COACH is to provide an environment to design emmbedded systems and
     28HPC applications on FPGA devices. The COACH framework will allow designer to explore various
     29software/hardware partitioning scenario of the target application through timing and functional
    3130simulations and to generate automatically both the software and the
    32 synthesizable description of the hardware.
    33 The main topics of the project are:
     31synthesizable description of the hardware. Exploration and design are mainly
     32driven by throughput, latency and/or power consumption criteria.
     33The main contributions of the project are:
    3434\begin{itemize}
    35 \item Design space exploration: It consists in analysing the application
    36 runnig on FPGA, defining the target technology (SoC, MPSoC, ASIP, ...) and
    37 hardware/software partitioning of tasks depending on technology choice.
    38 This exploration is driven basically by throughput, latency and power
    39 consumption criteria.
    40 \item Micro-architectural exploration: When hardware components are
    41 required, the HLS tools of the framework generate them automatically. At
    42 this stage the framework provides various HLS tools allowing the
    43 micro-architectural space design exploration. The exploration criteria are
    44 also throughput, latency and power consumption.
    45 % FIXME
    46 %CA At this stage, preliminary source-level transformations will be
    47 %CA required to improve the efficiency of the target component.
    48 %CA COACH will also provide such facilities, such as automatic parallelization
    49 %CA and memory optimisation.
    50 \item Performance measurement: For each point of design space exploration,
    51 metrics of criteria are available such as throughput, latency, power
    52 consumption, area, memory allocation and data locality.
    53 They are evaluated using virtual prototyping, estimation or analysing
    54 methodologies.
    55 \item Targeted hardware technology: The COACH description of system is
    56 independent of the FPGA family.
    57 Every point of the design exploration space can be implemented on any FPGA
    58 having the required resources.
    59 Basically, COACH handles both Altera and Xilinx FPGA families and supports
    60 3 generic target architectures:
    61 the COACH architecture based on the MIPS of the TSAR ANR project and a VCI ring bus,
    62 the Altera architecture based on the NIOS and AVALON bus,
    63 the Xilinx architecture based on the MICROBLAZE and OPB bus.
     35\item Targeted hardware architecture and technology:
     36COACH will handle both Altera and Xilinx FPGA technologies. COACH will define
     37architectural templates that can be customized by additional dedicated coprocessors and ASIPs.
     38The parameters of the architectural templates will be the number of CPU, the operating  system... 
     39%the coprocessors, the number and the size of the FIFO communication channels
     40Basically, the 3 following architectural templates will be provided:
     41A COACH architectural template based on the MIPS of the TSAR ANR project and a VCI ring bus,
     42An Altera architectural template based on the NIOS and the AVALON bus,
     43%FIXME
     44% The following point has to be confirmed by XILINX
     45% Microblaze+OPB => ARM+Amba ???
     46A Xilinx architectural template based on the MICROBLAZE and the OPB bus.
     47Moreover, the specification of the application will be independant of both the template
     48architecture and the selected technology.
     49\item Design space exploration: The COACH environment will allow to select and parametrize
     50the target architecture, to define hardware/software partitioning and to profile the application.
     51For each point of design space exploration, metrics such as throughput, latency, power consumption,
     52area, memory allocation and data locality will be provided.
     53This criteria will be evaluated by using virtual prototyping and high-level estimation methodologies.
     54\item Hardware accelerators synthesis (HAS): COACH will allow to generate automatically hardware accelerators
     55when required. Hence, High-Level Synthesis (HLS) tools, ASIP design environement and
     56source-level transformations (loop transformations and memory optimisation) will be provided.
     57This will allow to further explore the micro-architectural design space.
    6458\end{itemize}
    65 As an extension of embedded system design, COACH deals also with High
    66 Performance Computing (HPC).
    67 In HPC, the kind of targeted application is an existing one running on PC.
    68 COACH helps designer to accelerate it by migrating critical parts into a
    69 SoC implemented on a FPGA plugged to the PC bus.\\
    70 Finally COACH will be developped under the General Public Licence for the software,
    71 and USAGE LIBRE NON COMMERCIAL for the COACH architecture.
     59%In HPC, the kind of targeted application is an existing one running on PC.
     60%COACH helps designer to accelerate it by migrating critical parts into a
     61%SoC implemented on a FPGA plugged to the PC bus.\\
     62%FIXME licence a speficier
     63The COACH environment will be designed to abstract the hardware as much as possible to the end user.
     64It will thus be mainly dedicated to system designers.
     65Finally COACH will be developped under the General Public Licence for the software tools.
     66and USAGE LIBRE NON COMMERCIAL for the COACH arhitecture.
     67%The COACH architectural templates will be freely distributed.
    7268%
    7369% verrous scientifiques et techniques
    7470\mbox{}\vspace*{.9ex}\par
    75 System design is a very complicated task and in this project we try to simplify it
    76 as much as possible. For this purpose we have to deal with the following scientific
    77 and technological barriers.
     71System design is a very complex task this project will simplify as much as possible.
     72For this purpose the following scientific and technological barriers will be addressed:
    7873\begin{itemize}
    79 \item The run frequency of the coprocessors generated by the HLS must respect
    80 accurately the system frequency given bt the processors and bus.
    81 \item HLS tools are sensitive to the style in which the algorithm is written
    82 and the domain they target. The HLS tools of COACH must have a common language
    83 and style to avoid engineering work to the designer.
    84 \item The main problem in HPC is in the communication between the PC and the SoC
    85 firstly at the efficiency level and secondly to eliminate enginnering effort to
    86 implement it.
     74\item The clock frequency of the coprocessors generated by the HLS must respect
     75the frequency of the processors and the system bus.
     76\item HLS tools are sensitive to the coding style of the input specification
     77and the domain they target (control vs. data dominated). The HLS tools of COACH must have a
     78common language and coding style to avoid engineering work to the designer.
     79\item The main problem in HPC comes from timing performance and implementation of the communication
     80between the PC and the FPGA.
     81%FIXME: a completer loop tranfrom?, ASIP?, ...
    8782\end{itemize}
    8883%
    … …  
    9186COACH is the result of the will of several laboratories to unify their know
    9287hows and skills in the following domains: Operating system and hardware
    93 communication (TIMA, SITI), SoC and MPSoC (LIP6 and TIMA), ASIP (IRISA) and
    94 HLS (LIP6, Lab-STIC and LIP).
    95 So COACH does not starts from scratch but it relies
    96 on SocLib~\cite{soclib} with the MUTEX and DNA/OS operating system for
    97 system prototyping,
    98 on BEE~\cite{bee}, GAUT~\cite{gaut08}, ROMA~\cite{roma}, SYNTOL~\cite{syntol}
    99 and UGH~\cite{ugh08} for HLS.
    100 The project objective is to integrate and enhance these various tools into
    101 a unique free framework masking as much as possible these domains and its
    102 different tools to the system designer.  The main steps of this projects are:
    103 1) Definition of the designer input as set of communicating tasks, each
    104 task beeing described in C++ language.
    105 2) Definition of the xhls format, an internal format for representing a
    106 task.
    107 3) Developping a GCC addon for generating the xhls date from a C++ task
    108 description.
    109 4) Adapting the existing HLS tools to read and write xhls format and
    110 enhancing them. This allows to swap from one tool to the other and
    111 chain them.
    112 5) Modifying the Design System Explorator of SocLib to let the designer
    113 to explore the design space and then to generate the bitstream to
    114 the target FPGA.
     88communication (TIMA and CITI), SoC and MPSoC (LIP6 and TIMA), ASIP (IRISA) and
     89HLS (LIP6 and Lab-STICC)  and loop tranformations (LIP).
     90COACH does not start from scratch but relies
     91on the SocLib platform~\cite{soclib} with the MUTEX and DNA/OS operating system for
     92SoC and MPSoC prototyping, on GAUT~\cite{gaut08} and UGH~\cite{ugh08} for HLS, on
     93ROMA~\cite{roma} for ASIP, on SYNTOL~\cite{syntol} and BEE~\cite{bee} for loop tranformations.
     94The project objective is to enhance and seamlessly integrate these tools into
     95a unique open source framework.
     96%masking these domains and its different tools to the system designer.
     97The main steps of this project are:
     981) Definition of the user inputs: application description as set of communicating tasks, each
     99task beeing described in C++ language; architectural template with its parameters; design constraints.
     1002) Definition of the internal \xcoach format for representing a task.
     1013) Development of a GCC pluggin for generating the \xcoach representation of a C++ task.
     1024) Adaptation of the existing HLS tools to read and write the \xcoach format. This will allow to
     103swap from one tool to an other one and to chain them.
     1045) Modification of the Design System eXplorator DSX of the SocLib platform to let the user
     105explore the design space and then to generate the bitstream.
     106%FIXME : a completer
    115107\par
    116 The role of the industrials BUL, THALES, XXX, XXX is to provide real
    117 benchmark to guide the design of framework and prove that COACH is
     108The role of the industrial partners BULL, THALES, XXX is to provide real
     109benchmarks to guide the design of the framework and to prove that COACH is
    118110usuable and cover a large spectrum of applications.
    119111%
    120112% les retombées scientifiques, techniques et économiques
    121113\vspace*{.9ex}\par
    122 The main scientific contributions of the project are
    123 firstly to make high level synthesis an elementary tool of system design,
    124 seconly to unify various synthesis techniques (same input and output formats)
     114The main scientific contributions of the project are:
     115to make high-level synthesis an elementary tool of system design,
     116to unify various synthesis techniques (same input and output formats)
    125117allowing the designer to swap from one to an other and even to chain them
    126118without rewritting effort,
    127 and finally to provide a system description independent of the target
    128 architecture and the FPGA family.
     119to provide a system description independent of the target architecture and
     120the FPGA family.
    129121\par
    130122The market of embedded system and HPC is about 4,600 M\$ today and is
    … …  
    133125by major companies that can support the very high Non Recurring Engineering (NRE)
    134126costs involved in designing such system.
    135 Small companies can only be present in this market with GPUs based solutions that have
     127Small and medium companies can only be present in this market with GPUs based solutions that have
    136128low NRE costs but limit the application domains.\\
    137129COACH reduces the NRE costs to the design costs (the FPGA device being only a few
    … …  
    142134that will be able to propose embedded system and accelerating solutions for standard
    143135software applications with acceptable prices.\\
    144 The two major FPGA companies Altera and Xilinx expect thus by supporting
     136The two major FPGA companies Altera and Xilinx expect this by supporting
    145137and participating in this project.
    146138
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