source: anr/section-1.tex @ 27

% les objectifs globaux, 
During these last decades, the design of complex digital systems is more and more reserved 
high volume market. Indeed, the design and fabrication costs of submicronic technologies reach highs 
due to increasing NRE (Non Recurring-Engineering) charges. The market of digital systems is about 
4,600 M\$ today and is estimated to 5,600 M\$ in 2012.
Digital system design has been investigated since eighties by using Applications 
Specific Integrated Circuits (ASIC), Digital Signal Processing (DSP) and parallel computing on 
multiprocessor machines or networks.  Other technologies appeared like Very Large 
Instruction Word (VLIW) and Application Specific Instruction Processors (ASIP). 
Unfortunatly, the ever growing applications' complexity involves higher integration of heterogeneous technologies 
and thus requieres to design System-on-Chip (SoC) and Multi-Processors SoC (MPSoC).
Nowadays, Field Programmable Gate Arrays (FPGA), such like Virtex5 from Xilinx
and Stratix4 from Altera, can implement a complete SoC with multiple processors and
several coprocessors for less than 10K euros per device.
In addition, Electronic System Level (ESL) design methodologies (Virtual Prototyping, 
Co-design, High-Level Synthesis...) become mature and allow to automate the design of digital 
systems and to drastically decrease their cost in terms of man power.
Thus, coupling both FPGA and ESL methodologies will soon allow small and medium 
enterprises (SMEs) and major companies to get into new, low and medium volume markets, 
to design highly innovative devices and to prototype complete digital systems.
\par
The objective of COACH is to provide a consolidated flow, integrated and optimized for the design of
complex digital systems on FPGA devices.  A digital system is an application integrated into one or 
several chips. These chips can be embedded in devices such as a personal digital assistant (PDA), 
ambiant computing component, wireless sensor network (WSN). They can also be used on a board connected 
to a PC to accelerate an application like in High-Performance Computing (HPC) and in High-Speed Signal 
Processing (HSSP).

COACH will reduce the NRE costs to the design costs (the FPGA device being only a few
K\euro) and reduces drastically them. So one can expect that tools targeting FPGA and dedicated to software developpers
will gain market share over Multi-core CPUs and GPUs HPC based solutions.
Moreover this market can also be boosted by small and even very small new companies
that will be able to propose embedded system and accelerating solutions for standard
software applications with acceptable prices.\\

The main idea is to increase the design productivity by selecting a given flexible architectural template 
and targeting the area of complex digital systems. This project involves the development of methodologies and 
tools that allows an efficient design space exploration (processors, coprocessors, memories and buses or NoC) 
of whole systems, by taking into account different application constraints (power consumption, throughput, latency...). 
The project will also optimize an 
important interface, usually not taken into account, between the high-level synthesis and the implementation 
techniques on physical targets and the associated low level tools (logic synthesis and compilation). 
The flow will allow, from a high-level specification (written in C language), to estimate, analyze, optimize the 
performances and finally implement a real architecture. The COACH framework will allow the designer to explore various 
software/hardware partitioning scenario of the target application through timing and functional simulations and to 
generate automatically both the software and the synthesizable description of the hardware. 

%verrous scientifiques et techniques
The main contributions of the project are:
\begin{itemize} 
\item Targeted hardware architecture and technology: 
COACH will handle both Altera and Xilinx FPGA technologies. COACH will define 
architectural templates that can be customized by additional dedicated coprocessors and ASIPs.
The parameters of the architectural templates will be the number of CPU, the operating  system...  
%the coprocessors, the number and the size of the FIFO communication channels 
Basically, the 3 following architectural templates will be provided:
A COACH architectural template based on the MIPS of the TSAR ANR project and a VCI ring bus,
An Altera architectural template based on the NIOS and the AVALON bus,
%FIXME
% The following point has to be confirmed by XILINX
% Microblaze+OPB => ARM+Amba ???
A Xilinx architectural template based on the MICROBLAZE and the OPB bus. 
Moreover, the specification of the application will be independant of both the template 
architecture and the selected technology. 
\item Design space exploration: The COACH environment will allow to select and parametrize 
the target architecture, to define hardware/software partitioning and to profile the application. 
For each point of design space exploration, metrics such as throughput, latency, power consumption, 
area, memory allocation and data locality will be provided.
This criteria will be evaluated by using virtual prototyping and high-level estimation methodologies.
\item Hardware accelerators synthesis (HAS): COACH will allow to generate automatically hardware accelerators 
when required. Hence, High-Level Synthesis (HLS) tools, ASIP design environement and 
source-level transformations (loop transformations and memory optimisation) will be provided. 
This will allow to further explore the micro-architectural design space.
HLS tools are sensitive to the coding style of the input specification and the domain they target (control vs. 
data dominated). The HLS tools of COACH will support a common language and coding style to avoid engineering 
work to the designer.
\item Communication interface: Coach will define and implement HW/SW communication management and define APIs
enabling communication between processors, processor/coprocessors,  FPGA and PC.
\end{itemize}
%In HPC, the kind of targeted application is an existing one running on PC.
%COACH helps designer to accelerate it by migrating critical parts into a
%SoC implemented on a FPGA plugged to the PC bus.\\
%FIXME licence a speficier

COACH will be designed to abstract the hardware as much as possible to the end user.
It will thus be mainly dedicated to system designers.



% le programme de travail
\vspace*{.9ex}\par

The COACH project targets fundamental issues related to design methodologies for 
digital systems by providing estimation, exploration and design tools targeting both 
performance and power optimization at all the abstraction levels of the flow (system, 
architecture, algorithm and logic).

To reach this ambitious aim, this project will lean on the experience and the complementariness 
of partners in the following domains: Operating system and hardware
communication (TIMA and CITI), SoC and MPSoC (LIP6 and TIMA), ASIP (IRISA) and
HLS (LIP6 and Lab-STICC)  and loop tranformations (LIP).
COACH does not start from scratch but relies
on the SocLib platform~\cite{soclib} with the MUTEX and DNA/OS operating system for
SoC and MPSoC prototyping, on GAUT~\cite{gaut08} and UGH~\cite{ugh08} for HLS, on 
ROMA~\cite{roma} for ASIP, on SYNTOL~\cite{syntol} and BEE~\cite{bee} for loop tranformations.

The project objective is to enhance and seamlessly integrate these tools into
a unique open source framework. 
The main steps of this project are:
1) Definition of the user inputs: application description as set of communicating tasks, each
task beeing described in C++ language; architectural template with its parameters; design constraints. 
2) Definition of the internal \xcoach format for representing a task.
3) Development of a GCC pluggin for generating the \xcoach representation of a C++ task.
4) Adaptation of the existing HLS tools to read and write the \xcoach format. This will allow to 
swap from one tool to an other one and to chain them.
5) Modification of the Design System eXplorator DSX of the SocLib platform to let the user
explore the design space and then to generate the bitstream.
%FIXME : a completer
\par

The two major FPGA companies Altera and Xilinx expect this by supporting
and participating in this project.
The role of the industrial partners BULL, THALES, XXX is to provide real
benchmarks to guide the design of the framework and to prove that COACH is
usuable and cover a large spectrum of applications.

The COACH arhitectural templates will be freely distributed for non commercial use.
COACH will be developped under the General Public Licence for the software tools.