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1% les objectifs globaux,
2The market of digital systems is about 4,600 M\$ today and is estimated to
35,600 M\$ in 2012. However the ever growing application complexity involves
4integration of heterogeneous technologies and requires the design of
5complex Multi-Processors System on Chip (MPSoC).
6\\
7During the last decade, the use of ASICs (Application Specific
8Integrated Circuits) appeared to be more and more reserved to high volume markets, because
9the design and fabrication costs of such components exploded, due to increasing NRE (Non
10Recurring-Engineering) costs.
11Fortunately, FPGA (Field Programmable Gate Array) components, such as the
12Virtex5 family from \xilinx or the Stratix4 family from \altera, can nowadays
13implement a complete MPSoC with multiple processors and several dedicated
14coprocessors for a few Keuros per device.
15\\
16Many applications are initially captured
17algorithmically in High-Level Languages (HLLs) such as C/C++. This has led to growing interest
18in tools that can provide an implementation path directly from HLLs to hardware.
19Thus, Electronic System Level (ESL) design methodologies (Virtual Prototyping,
20Co-design, High-Level Synthesis...) are now mature and allow the automation of
21a system-level design flow. Unfortunately, ESL tool development to date has primarily focused
22on the design of hard-wired devices i.e. ASICs and ASSPs (Application Specific Standard Product).
23However, the increasing sophistication of FPGAs has accelerated the need for FPGA-based ESL design
24methodologies. ESL methodologies hold the promise of streamlining the design approach by accepting
25designs written in the C/C++ language and implementing the function directly into FPGA.
26We believe that coupling FPGA technologies and ESL methodologies
27will allow both SMEs (Small and Medium Enterprise) and major companies to design innovative
28devices and to enter new, low and medium volume markets.
29Furthermore, today there is an increasing industrial interest into IC
30that integrates both hardwired CPU cores or MPSoC and a configurable area (FPGA)
31such as the ATOM E600C chip (Intel).
32In few a years, one can expect that such chips will become current. Even standard
33general purpose CPU cores will contains a configurable area
34bringing an explosion in low and medium volume markets.
35\parlf
36The objective of COACH is to provide an integrated design flow for the design of
37multi-processors digital systems targeting FPGA devices.
38It will be dedicated to system/software designers, and hide as much as possible
39the hardware characteristics to the end-user.
40COACH will mainly target three kinds of digital systems:
411) embedded and autonomous application such as  personal digital assistants (PDA),
42   ambient computing components, or wireless sensor networks (WSN);
432) PCI/E extension boards connected to a PC to accelerate a specific application,
44   it is the domain of High-Performance Computing (HPC) and High-Speed Signal Processing (HSSP);
453) sub-system application for generating an IP to a larger system.
46\parlf
47%verrous scientifiques et techniques
48The COACH environment will integrate several hardware and software technologies:
49\begin{description}
50\item[Design Space Exploration:]
51    The COACH environment will allow to describe an application as a process
52        network i.e. a set of tasks communicating through FIFO channels.
53        COACH will allow to map the application on a shared-memory, MPSoC architecture.
54    It will permit to easily explore the design space to help the system designer
55        to define the proper hardware/software partitioning of the application.
56    For each point in the design space, metrics such as throughput, latency, power
57    consumption, silicon area, memory allocation and data locality will be provided.
58\item[Hardware Accelerators Synthesis (HAS):]
59    COACH will allow the automatic generation of hardware accelerators when required.
60    Hence, High-Level Synthesis (HLS) tools, Application Specific Instruction Processor
61    (ASIP) design environments and source-level transformation tools (loop transformations
62    and memory optimization) will be provided.
63    This will allow further exploration of the micro-architectural design space.
64    HLS tools are sensitive to the coding style of the input specification and the domain
65    they target (control vs. data dominated).
66    The HLS tools of COACH will support a common language and coding style to avoid
67    re-engineering by the designer.
68\item[Platform based design:] 
69    COACH will handle both \altera and \xilinx FPGA devices.
70    COACH will define architectural templates that can be customized by adding
71    dedicated coprocessors and ASIPs and by fixing template parameters such as
72    the number of embedded processors, the number and size of embedded memory banks
73    or the embedded operating system.
74    However, the specification of the application will be independent of both the
75    architectural template and the target FPGA device.
76    Basically, the following three architectural templates will be provided:
77    \begin{enumerate}
78    \item A Neutral architectural template based on the SoCLib IP core library and the
79      VCI/OCP communication infrastructure.
80    \item An \altera architectural template based on the \altera IP core library, the
81      AVALON system bus and the NIOS processor.
82    \item A \xilinx architectural template based on the \xilinx IP core library,
83      the \xilinxbus system bus and the \xilinxcpu processor.
84    \end{enumerate}
85\item[Hardware/Software communication middleware:]
86    COACH will implement an homogeneous HW/SW communication infrastructure and
87    communication APIs (Application Programming Interface), that will be used for
88    communications between software tasks running on embedded processors and
89    dedicated hardware coprocessors.
90\item[Interaction with the industrial world:]
91    COACH will not be a closed framework but it will be opened to the industrial
92    world by using the IP-XACT format \cite{IP-XACT-08} for describing the components of the
93    architectural template and by providing the IP-XACT description of the generated MPSoC.
94    This should facilitate the enhancement of the architectural template with IP and the
95    integration of the IP produced by COACH in larger design.
96\end{description}
97%From the end user point of view, the specification of the application will be
98%independant from both the architectural template and from the selected FPGA
99%family.
100\parlf
101% le programme de travail
102%The COACH project targets fundamental issues related to design methodologies for
103%digital systems by providing estimation, exploration and design tools targeting both
104%performance and power optimization at all the abstraction levels of the flow (system,
105%architecture, algorithm and logic).
106To reach this ambitious goal, the project will rely on the experience and the
107%complementariness
108synergy of the partners in the following domains:
109Operating system and communication middleware (\tima, \upmc),
110MPSoC architectures (\tima, \ubs, \upmc),
111ASIP architectures (\inria),
112High Level Synthesis (\tima, \ubs, \upmc), and compilation (\lip),
113HPC (\bull, \thales, \lip), tools integration in IP-XACT flow (\mds).
114\\
115The COACH project does not start from scratch.
116It relies
117on the Magillem industrial platform for the integration into IP-XACT flows,
118on the SoCLib platform~\cite{soclib} for prototyping and operating systems (DNA/OS),
119on the GAUT~\cite{gaut08} and UGH~\cite{ugh08} tools for HLS,
120on the ROMA~\cite{roma, RAFFIN:2010:INRIA-00539874:1} project for ASIP,
121on the SYNTOL~\cite{syntol} and BEE~\cite{bee} tools for source-level analysis and
122transformations,
123and on the \xilinx and \altera IP core libraries.
124Finally it will use the \xilinx and \altera logic and physical synthesis tools
125to generate the FPGA configuration bitstreams.
126%The main development steps of the COACH project are:
127%\begin{enumerate}
128%   \item Definition of the end user inputs:
129%    The coarse grain parallelism of the application will be described as a communicating
130%    task graph, each task being described in C language.
131%    Similarly the architectural templates with their parameters and the design constraints
132%    will be specified.
133%  \item Definition of an internal format for representing task.
134%  \item Development of the GCC pluggin for generating the internal format of a
135%    C task.
136%  \item Adaptation of the existing HAS tools (BEE, SYNTOL, UGH, GAUT) to read and write
137%    the internal format. This will allow to swap from one tool to another one, and to
138%    chain them if necessary.
139%  \item Modification of the DSX tool (Design Space eXplorer) of the SocLib
140%    platform to generate the bitstream for the various FPGA families and architectural
141%    templates.
142%  \item Development of new tools such as ASIP compiler, HPC design environment and
143%    dynamic reconfiguration of FPGA devices.
144%\end{enumerate}
145\parlf
146The role of the industrial partners \bull, \thales and \mds is to provide
147real use cases to benchmark the COACH design environment and to analyze the designer productivity
148improvements.
149\parlf
150The COACH project will deliver an open and freely distributed infrastructure.
151The architectural templates and most of the software tools will be distributed under the
152GPL-like license.
153The VHDL synthesizable models for the neutral architectural template
154will also be freely available for non commercial use.
155For industrial exploitation the technology providers are ready to propose commercial licenses,
156directly to the end user, or through a third party.
157\parlf
158\mustbecompleted{LIST NON A JOUR}
159The major FPGA companies (\xilinx and \altera) have expressed their interest for
160this project.
161Finally, the COACH project is already supported by a large number of SMEs, as demonstrated by the
162"letters of interest" (see Annex B), that have been collected during the preparation of the project :
163ADACSYS, MDS, INPIXAL, CAMKA System, ATEME, ALSIM, SILICOMP-AQL,
164ABOUND Logic, EADS-ASTRIUM.
165
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