Changeset 337 for anr/section-1.tex

Timestamp:

Jan 31, 2011, 2:50:29 PM (13 years ago)

Author:

coach

Message:

language modifications (Paul)

File:

• anr/section-1.tex (modified) (6 diffs)

anr/section-1.tex

@@ -1 +1 @@
 % les objectifs globaux, 
 The market of digital systems is about 4,600 M\$ today and is estimated to
-5,600 M\$ in 2012. However the ever growing applications complexity involves
+5,600 M\$ in 2012. However the ever growing application complexity involves
 integration of heterogeneous technologies and requires the design of
 complex Multi-Processors System on Chip (MPSoC).
@@ -23 +23 @@
 However, the increasing sophistication of FPGAs has accelerated the need for FPGA-based ESL design 
 methodologies. ESL methodologies hold the promise of streamlining the design approach by accepting 
-designs written in C/C++ language and implementing the function straight into FPGA. 
+designs written in the C/C++ language and implementing the function directly into FPGA. 
 We believe that coupling FPGA technologies and ESL methodologies
 will allow both SMEs (Small and Medium Enterprise) and major companies to design innovative
 devices and to enter new, low and medium volume markets.
-Furthermore, today there is an increasing industrial interest to IC
+Furthermore, today there is an increasing industrial interest into IC
 that integrates both hardwired CPU cores or MPSoC and a configurable area (FPGA)
-such as ATOM E600C (Intel).
-Probably in few years, one can expect that such chips will become current and even standard
-general purpose CPU cores will contains a configurable area%
-%paul
+such as the ATOM E600C chip (Intel).
+In few a years, one can expect that such chips will become current. Even standard
+general purpose CPU cores will contains a configurable area
 bringing an explosion in low and medium volume markets.
 \parlf
@@ -60 +59 @@
     COACH will allow the automatic generation of hardware accelerators when required.
     Hence, High-Level Synthesis (HLS) tools, Application Specific Instruction Processor
-    (ASIP) design environment and source-level transformation tools (loop transformations
+    (ASIP) design environments and source-level transformation tools (loop transformations
     and memory optimization) will be provided.
     This will allow further exploration of the micro-architectural design space.
@@ -71 +70 @@
     COACH will define architectural templates that can be customized by adding
     dedicated coprocessors and ASIPs and by fixing template parameters such as
-    the number of embedded processors, the number of sizes of embedded memory banks
+    the number of embedded processors, the number and size of embedded memory banks
     or the embedded operating system.
     However, the specification of the application will be independent of both the
@@ -106 +105 @@
 %architecture, algorithm and logic).
 To reach this ambitious goal, the project will rely on the experience and the
-complementariness of partners in the following domains:
+%complementariness
+synergy of the partners in the following domains:
 Operating system and communication middleware (\tima, \upmc),
 MPSoC architectures (\tima, \ubs, \upmc),
 ASIP architectures (\inria),
 High Level Synthesis (\tima, \ubs, \upmc), and compilation (\lip),
-HPC (\bull, \thales), tools integration in IP-XACT flow (\mds).
+HPC (\bull, \thales, \lip), tools integration in IP-XACT flow (\mds).
 \\
 The COACH project does not start from scratch.
@@ -160 +160 @@
 this project.
 Finally, the COACH project is already supported by a large number of SMEs, as demonstrated by the 
-"letters of interest" (see Annex B), that have collected during the preparation of the project :
+"letters of interest" (see Annex B), that have been collected during the preparation of the project :
 ADACSYS, MDS, INPIXAL, CAMKA System, ATEME, ALSIM, SILICOMP-AQL,
 ABOUND Logic, EADS-ASTRIUM.