source: anr/section-2.2.tex @ 239

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Paul coquilles

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1% Relevance of the proposal
2The COACH proposal addresses directly the \emph{Embedded Systems} item of
3the ARPEGE program. It aims to propose solutions to the societal/economical challenges by
4providing SMEs novel design capabilities enabling them to increase their
5design productivity with design exploration and synthesis methods that are placed on top
6of the state-of-the-art methods.
7This project proposes an open-source framework for mapping multi-tasks software applications
8on Field Programmable Gate Array circuits (FPGA).
9%%%
10\parlf
11COACH will contribute to build an open development and run-time
12environment, including communication middleware and tools to support
13developers in the production of embedded software, through all phases of the software lifecycle,
14from requirements analysis downto deployment and maintenance.
15More specifically, COACH focuses on:
16\begin{itemize}
17\item High level methods and concepts (esp. requirements and architectural level) for system
18design, development and integration, addressing complexity aspects and modularity.
19\item Open and modular development environments, enabling flexibility and extensibility by
20means of new or sector-specific tools and ensuring consistency and traceability along the
21development lifecycle.
22\item Light/agile methodologies and adaptive workflow providing a dynamic and adaptive
23environment, suitable for co-operative and distributed development.
24\end{itemize}
25COACH outcome will contribute to strengthen Europe's competitive position by developing
26technologies and methodologies for product development, focusing (in compliance with the
27%scope of the above program) on technologies, engineering methodologies, novel tools,
28%methods which facilitate resource use efficiency. The approaches and tools to be developed
29%in COACH will enable new and emerging information technologies for the development,
30%methods which facilitate resource use efficiency. The COACH approaches and tools
31scope of the above program) on technologies, engineering methodologies, novel tools
32which facilitate resource use efficiency. The COACH approaches and tools
33will enable new and emerging information technologies for the development,
34manufacturing and integration of devices and related software into end-products.
35%%%
36\parlf\noindent
37The COACH project will benefit from a number of previous recent projects:
38\begin{description}
39  \item[SOCLIB]
40    The SoCLib ANR platform (2007-2009) is an open infrastructure developped by
41    10 academic laboratories (TIMA, LIP6, Lab-STICC, IRISA, ENST, CEA-LIST, CEA-LETI, CITI, INRIA-Futurs, LIS) and 6
42    industrial companies (Thales Communications, Thomson R\&D, STMicroelectronics, Silicomp, MDS, TurboConcept).
43    It supports system level virtual prototyping of shared memory, multi-processors
44    architectures, and provides tools to map multi-tasks software application on these
45    architectures, for reliable performance evaluation.
46    The core of this platform is a library of SystemC simulation models for
47    general purpose IP cores such as processors, buses, networks, memories, IO controller.
48    The platform provides also embedded operating systems and software/hardware
49    communication middleware.
50    The synthesisable VHDL models of IPs are not part of the SoCLib platform, and
51    COACH will enhance SoCLib by providing the synthesisable VHDL models required
52    for FPGA synthesis.
53  \item[ROMA] The ROMA ANR project \cite{roma}
54    involving IRISA (CAIRN team), LIRMM, CEA List, THOMSON France R\&D,
55    proposes to develop a reconfigurable processor, exhibiting high
56    silicon density and power efficiency, able to adapt its computing
57    structure to computation patterns that can be speed-up and/or
58    power efficient.  The ROMA project study a pipeline of
59    evolved low-power coarse grain reconfigurable operators to avoid
60    traditional overhead, in reconfigurable devices, related to the
61    interconnection network.  The project will borrow from the ROMA
62    ANR project and the ongoing joint INRIA-STMicro
63    Nano2012 project to adapt existing pattern extraction algorithms
64    and datapath merging techniques to ASIP synthesis.
65%    and datapath merging techniques to the synthesis of customized
66%    ASIP processors.
67  \item[TSAR]
68     The TSAR MEDEA+ project (2008-2010) involving BULL, THALES and \upmc targets the design of a
69%    The TSAR MEDEA+ project (2008-2010) targets the design of a
70    scalable, coherent shared memory, multi-cores processor architecture, and uses the SoCLib
71    plaform for virtual prototyping. The COACH project will benefit from the synthesizable VHDL
72    models developped in the framework of TSAR (MIPS32 processor core, and RING interconnect).
73  \item[BioWic]
74    On the HPC application side, we also hope to benefit from the experience in
75    hardware acceleration of bioinformatic algorithms/workfows gathered by the
76    CAIRN group in the context of the ANR BioWic project (2009-2011), so as to
77    be able to validate the framework on real-life HPC applications.
78\end{description}
79%%%
80\parlf\noindent
81The laboratories involved in the COACH project have a well estabished expertise
82%in the following domains:
83in the domains:
84\begin{itemize}
85  \item 
86    In the field of High Level Synthesis (HLS), the project
87    leverages on know-how acquired over the last 15 years with the GAUT~\cite{gaut08} project
88    developped by the \ubs laboratory, and with the UGH~\cite{ugh08} project developped
89    by the \upmc and \tima laboratories.
90  \item
91    Regarding system level architecture, the project is based on the know-how
92    acquired by the \upmc and \tima laboratories in the framework of various projects 
93    in the field of communication architectures for shared memory multi-processors systems
94    (COSY~\cite{cosy}, DISYDENT~\cite{disydent05} or DSPIN~\cite{dspin08} of MEDEA-MESA).
95    As an example, the DSPIN project is now used in the TSAR project.
96  \item
97    Regarding Application Specific Instruction Processor (ASIP) design, the
98    CAIRN group at INRIA Rennes -- Bretagne Atlantique benefits from several years of
99    expertise in the domain of retargetable compiler
100    (Armor/Calife~\cite{CODES99} since 1996, and the Gecos
101    compilers~\cite{ASAP05} since 2002).
102\item
103    In the field of compilers, the Compsys group was founded in 2002
104    by several senior researchers with experience in
105    high performance computing and automatic parallelization. They have been
106    among the initiators of the polyhedral model, a theory which serve to
107    unify many parallelism detection and exploitation techniques for regular
108    programs. It is expected that the techniques developped by Compsys for
109    parallelism detection, scheduling, process construction and memory management
110    will be very useful as a front-end for the a high-level synthesis tools.
111\end{itemize}
112%%%
113\parlf\noindent
114The COACH project answers to several of the challenges found in different axis of the
115call for proposals.%Keywords of the call are indicated below in italic writing.
116\begin{description}
117\item[Axis 1] \textit{Architectures des syst\`{e}mes embarqu\'{e}s} \\
118COACH will address new embedded systems architectures by allowing the design of
119Multi-Core Systems-on-Chip (possibly heterogeneous) on FPGA according to the design
120constraints and objectives (real-time, low-power). It will permit designing  complex SoC
121based on IP cores (memory, peripherals, network controllers, communication processors),
122running Embedded Software, as well as an Operating System with associated middleware and
123API and using hardware accelerator automatically generated. It will also permit to use
124efficiently different dynamic system management techniques and re-configuration mechanisms.
125\textbf{Thereby COACH well corresponds to axis 1}.
126%
127\item[Axis 2] \textit{Infrastructures pour l'Internet, le calcul intensif ou les services} \\
128COACH will address High-Performance Computing (HPC) by helping designers to accelerate an
129application running on a PC by migrating critical parts into a SoC implemented on an FPGA
130plugged to the PC bus (through a communication link like PCI/X). COACH will reduce the designer
131effort through the development of tools that translate high level language programs to FPGA
132configurations. Moreover, Dynamic Partial Reconfiguration will be used for improving HPC performance
133as well as reducing the required area.
134\textbf{Thereby COACH partially corresponds to axis 2}.
135%
136% IA2PC: comme ce sont des axes tertiaire, il faut faire + court que primaire et
137% IA2PC: secondaire.
138%VERS 3
139%\item[Axis 3] \textit{Robotique et contr\^{o}le/commande} \\
140%Manufacturing technology employs more and more SoC.
141%COACH will permit to design such complex digital systems.
142%\textbf{Thereby COACH indirectly answers to axis 3 too}.
143
144
145%\item[Axis 3 \& 5] \textit{Robotique et contr\^{o}le/commande} and \textit{S\'{e}curit\'{e} et suret\'{e}} \\
146%VERS 1
147%Future control applications employ more and more SoC.
148%Application domains for such systems are for example the automotive domain, as well as the
149%aerospace and avionics domains.
150%In all cases, high performance and real time requirements are combined with
151%requirements to low power, low temperature, high dependability, and low cost.\\
152%Similary manufacturing, security and safety technologies require also more and more
153%computation power.
154%VERS 2 pour gagner de la place
155%Manufacturing, controling, security and safety technologies employ more and more SoC.
156%COACH will permit to design such complex digital systems.
157%\textbf{Thereby COACH indirectly answers to axis 3 and 5 too}.
158
159%\end{description}
160
161\item [Axis 3] \textit {Robotique et contr\^{o}le/commande}:
162
163COACH will address robotic and control applications domains by
164allowing to design complex digital systems based on MPSoC architecture.
165Like in the consumer electronics domain, future control applications
166will employ more and more SoC for safety and security applications.
167Application domains for such systems are for example automotive, 
168aerospace or avionics domains (e.g. collision-detection, intelligent navigation...).
169Manufacturing technology will also increasingly need high-end vision analysis and high-speed
170robot control.
171\textbf{Thereby COACH indirectly answers to axis 3}.
172
173\item [Axis 5] \textit {S\'{e}curit\'{e} et suret\'{e}}:
174
175The results of the COACH project will help users to build cryptographic secure systems implemented in
176hardware or both in software/hardware in an effective way, substantially enhancing the
177process productivity of the cryptographic algorithms hardware synthesis, improving the
178quality and reducing the design time and the cost of synthesised cryptographic devices.
179\textbf{Thereby COACH indirectly answers to axis 5}.
180
181\end{description}
182
183% IA2PC: 1) je ne vois pas trop ce que ca fait la.
184% IA2PC: 2) c'est deja dans le 2.1 pour le small business.
185% IA2PC: 3) Pour le large business, on avait mis ca dans la premiere version et je pense
186% IA2PC     toujours que le large business est encore vise par COACH.
187% IA2PC     Alain a enleve toute reference sur ce large business. Sa raison est +
188% IA2PC     politico/stylistique: en parlant des 2 on n'est pas tres clair et on brouille
189% IA2PC     le message. Je partage assez son avis, la version actuelle est + claire que
190% IA2PC     celle d'avant. De plus on ne dit jamais que l'on ne vise pas les grosses
191% IA2PC     boites.
192% IA2PC
193% IA2PC Bref je serai assez pour enlever ce paragraphe, et ne pas faire reference au large
194% IA2PC business meme dans les section precedente. Par contre d'essayer de recaser le reste dans
195% IA2PC les sections precedentes.
196%
197% VERS 2 pour gagner de la place je l'enleve
198
199%PC2IA ok pas de probleme
200
201% COACH technologies can be used in both large and small business, as they will permit users to design
202% embedded systems which meet a wide range of requirements: from low cost and low power consuming
203% devices to very high speed devices, based on parallel computing. For enterprises that will use embedded
204% systems designed via the approaches and tools targeted by COACH, there is the potential for greater
205% efficiency, improved business processes and models. The net results: lower costs, faster response times,
206% better service, and higher revenue.
207%\parlf
208Finally, it is worth to note that this project covers priorities defined by the commission
209experts in the field of Information Technolgies Society (IST) for Embedded
210Systems: \textit{ $<<$Concepts, methods and tools for designing systems dealing with systems complexity
211and allowing to apply efficiently applications and various products on embedded platforms,
212considering resources constraints (delays, power, memory, etc.), security and quality
213services$>>$}.
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