Changeset 237 for anr/section-2.2.tex

Timestamp:

Feb 16, 2010, 5:24:12 PM (14 years ago)

Author:

coach

Message:

Paul coquilles

File:

• anr/section-2.2.tex (modified) (4 diffs)

anr/section-2.2.tex

@@ -52 +52 @@
     for FPGA synthesis.
   \item[ROMA] The ROMA ANR project \cite{roma}
-    involving IRISA (CAIRN team), LIRMM, CEA List THOMSON France R\&D,
+    involving IRISA (CAIRN team), LIRMM, CEA List, THOMSON France R\&D,
     proposes to develop a reconfigurable processor, exhibiting high
     silicon density and power efficiency, able to adapt its computing
     structure to computation patterns that can be speed-up and/or
-    power efficient.  The ROMA project study a pipeline-based of
+    power efficient.  The ROMA project study a pipeline of
     evolved low-power coarse grain reconfigurable operators to avoid
     traditional overhead, in reconfigurable devices, related to the
@@ -66 +66 @@
 %    ASIP processors.
   \item[TSAR]
-     The TSAR MEDEA+ project (2008-2010) involving BULL, THALES and the \upmc targets the design of a 
+     The TSAR MEDEA+ project (2008-2010) involving BULL, THALES and \upmc targets the design of a 
 %    The TSAR MEDEA+ project (2008-2010) targets the design of a 
     scalable, coherent shared memory, multi-cores processor architecture, and uses the SoCLib
@@ -118 +118 @@
 COACH will address new embedded systems architectures by allowing the design of 
 Multi-Core Systems-on-Chip (possibly heterogeneous) on FPGA according to the design 
-constraints and objectives (real-time, low-power). It will permit to design  complex SoC 
+constraints and objectives (real-time, low-power). It will permit designing  complex SoC 
 based on IP cores (memory, peripherals, network controllers, communication processors), 
 running Embedded Software, as well as an Operating System with associated middleware and 
@@ -126 +126 @@
 %
 \item[Axis 2] \textit{Infrastructures pour l'Internet, le calcul intensif ou les services} \\
-COACH will address High-Performance Computing (HPC) by helping designer to accelerate an 
+COACH will address High-Performance Computing (HPC) by helping designers to accelerate an 
 application running on a PC by migrating critical parts into a SoC implemented on an FPGA 
 plugged to the PC bus (through a communication link like PCI/X). COACH will reduce the designer