source: anr/section-2.2.tex @ 283

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1% Relevance of the proposal
2%The COACH proposal addresses directly the \emph{Embedded Systems} item of
3%the ARPEGE program.
4
5%PC => IA et ALain
6%J'aui déplacé le pargraphe ci dessous en conclusion de la section précédente 2.1
7
8%It aims to propose solutions to the societal/economical challenges by
9%providing SMEs novel design capabilities enabling them to increase their
10%design productivity with design exploration and synthesis methods that are placed on top
11%of the state-of-the-art methods.
12%This project proposes an open-source framework for mapping multi-tasks software applications
13%on Field Programmable Gate Array circuits (FPGA).
14%%%
15\parlf
16COACH will contribute to build an open design and run-time
17environment, including communication middleware and tools to support
18developers in the production of embedded software, through all phases of the software lifecycle,
19from requirements analysis downto deployment and maintenance.
20More specifically, COACH focuses on:
21\begin{itemize}
22\item High level methods and concepts (esp. requirements and architectural level) for system
23design, development and integration, addressing complexity aspects and modularity.
24\item Open and modular design environments, enabling flexibility and extensibility by
25means of new or sector-specific tools and ensuring consistency and traceability along the
26development lifecycle.
27\item Light/agile methodologies and adaptive workflow providing a dynamic and adaptive
28environment, suitable for co-operative and distributed development.
29\end{itemize}
30COACH outcome will contribute to strengthen Europe's competitive position by developing
31technologies and methodologies for product design, focusing (in compliance with the
32%scope of the above program) on technologies, engineering methodologies, novel tools,
33%methods which facilitate resource use efficiency. The approaches and tools to be developed
34%in COACH will enable new and emerging information technologies for the development,
35%methods which facilitate resource use efficiency. The COACH approaches and tools
36scope of the above program) on technologies, engineering methodologies, novel tools
37which facilitate resource use efficiency. The COACH approaches and tools
38will enable new and emerging information technologies for the development,
39manufacturing and integration of devices and related software into end-products.
40%%%
41\parlf\noindent
42The COACH project will benefit from a number of previous recent projects:
43\begin{description}
44  \item[SOCLIB]
45    The SoCLib ANR platform (2007-2009) is an open infrastructure developped by
46    10 academic laboratories (TIMA, LIP6, Lab-STICC, IRISA, ENST, CEA-LIST, CEA-LETI, CITI, INRIA-Futurs, LIS) and 6
47    industrial companies (Thales Communications, Thomson R\&D, STMicroelectronics, Silicomp, MDS, TurboConcept).
48    It supports system level virtual prototyping of shared memory, multi-processors
49    architectures, and provides tools to map multi-tasks software application on these
50    architectures, for reliable performance evaluation.
51    The core of this platform is a library of SystemC simulation models for
52    general purpose IP cores such as processors, buses, networks, memories, IO controller.
53    The platform provides also embedded operating systems and software/hardware
54    communication middleware.
55    The synthesisable VHDL models of IPs are not part of the SoCLib platform, and
56    COACH will enhance SoCLib by providing the synthesisable VHDL models required
57    for FPGA synthesis.
58  \item[ROMA] The ROMA ANR project \cite{roma}
59    involving IRISA (CAIRN team), LIRMM, CEA List, THOMSON France R\&D,
60    proposes to develop a reconfigurable processor, exhibiting high
61    silicon density and power efficiency, able to adapt its computing
62    structure to computation patterns that can be speed-up and/or
63    power efficient.  %The ROMA project study a pipeline of
64    %evolved low-power coarse grain reconfigurable operators to avoid
65    %traditional overhead, in reconfigurable devices, related to the
66    %interconnection network. 
67        The project will borrow from the ROMA
68    ANR project and the ongoing joint INRIA-STMicro
69    Nano2012 project to adapt existing pattern extraction algorithms
70    and datapath merging techniques to ASIP synthesis.
71%    and datapath merging techniques to the synthesis of customized
72%    ASIP processors.
73  \item[TSAR]
74     The TSAR MEDEA+ project (2008-2010) involving BULL, THALES and \upmc targets the design of a
75%    The TSAR MEDEA+ project (2008-2010) targets the design of a
76    scalable, coherent shared memory, multi-cores processor architecture, and uses the SoCLib
77    plaform for virtual prototyping. COACH will benefit from the synthesizable VHDL
78    models developped in the framework of TSAR (MIPS32 processor core, and RING interconnect).
79  \item[BioWic]
80    On the HPC application side, we also hope to benefit from the experience in
81    hardware acceleration of bioinformatic algorithms/workfows gathered by the
82    CAIRN group in the context of the ANR BioWic project (2009-2011), so as to
83    be able to validate the framework on real-life HPC applications.
84\end{description}
85%%%
86\parlf\noindent
87The laboratories involved in the COACH project have a well estabished expertise
88%in the following domains:
89in the domains:
90\begin{itemize}
91  \item 
92    In the field of High Level Synthesis (HLS), the project
93    leverages on know-how acquired over the last 15 years with the GAUT~\cite{gaut08} project
94    developped by the \ubs laboratory, and with the UGH~\cite{ugh08} project developped
95    by the \upmc and \tima laboratories.
96  \item
97    Regarding system level architecture, the project is based on the know-how
98    acquired by \upmc and \tima in the framework of various projects 
99    in the field of communication architectures for shared memory multi-processors systems
100    (COSY~\cite{cosy}, DISYDENT~\cite{disydent05} or DSPIN~\cite{dspin08} of MEDEA-MESA).
101    As an example, the DSPIN project is now used in the TSAR project.
102  \item
103    Regarding Application Specific Instruction Processor (ASIP) design, the
104    CAIRN group at INRIA Rennes -- Bretagne Atlantique benefits from several years of
105    expertise in the domain of retargetable compiler
106    (Armor/Calife~\cite{CODES99} since 1996, and the Gecos
107    compilers~\cite{ASAP05} since 2002).
108\item
109    In the field of compilers, the \lip Compsys group was founded in 2002
110    by several senior researchers with experience in
111    high performance computing and automatic parallelization. They have been
112    among the initiators of the polyhedral model, a theory which serve to
113    unify many parallelism detection and exploitation techniques for regular
114    programs. It is expected that the techniques developped by \lip for
115    parallelism detection, scheduling \cite{Feau:92aa,Feau:92bb},
116    process construction \cite{Feau:96} and memory management \cite{bee}
117    will be very useful as a front-end for HLS tools.
118\end{itemize}
119%%%
120\parlf\noindent
121The COACH project answers to several of the challenges found in different axis of the
122call for proposals.%Keywords of the call are indicated below in italic writing.
123\begin{description}
124\item[Axis 1] \textit{Architectures des syst\`{e}mes embarqu\'{e}s} \\
125COACH will address new embedded systems architectures by allowing the design of
126Multi-Core Systems-on-Chip (possibly heterogeneous) on FPGA according to the design
127constraints and objectives (real-time, low-power). It will permit designing  complex SoC
128based on IP cores (memory, peripherals...),
129running Embedded Software, as well as an Operating System with associated middleware and
130API and using hardware accelerator automatically generated. It will also permit to use
131efficiently different dynamic system management techniques and re-configuration mechanisms.
132\textbf{Thereby COACH well corresponds to axis 1}.
133%
134\item[Axis 2] \textit{Infrastructures pour l'Internet, le calcul intensif ou les services} \\
135COACH will address High-Performance Computing (HPC) by helping designers to accelerate an
136application running on a PC.
137By providing tools that translate high level language programs to FPGA
138configurations, COACH will allow to easily migrate critical parts into an FPGA plugged to the
139PC bus (through a communication link like PCI/X).
140Moreover, Dynamic Partial Reconfiguration will be used for improving HPC performance
141as well as reducing the required area.
142\textbf{Thereby COACH partially corresponds to axis 2}.
143%
144% IA2PC: comme ce sont des axes tertiaire, il faut faire + court que primaire et
145% IA2PC: secondaire.
146%VERS 3
147%\item[Axis 3] \textit{Robotique et contr\^{o}le/commande} \\
148%Manufacturing technology employs more and more SoC.
149%COACH will permit to design such complex digital systems.
150%\textbf{Thereby COACH indirectly answers to axis 3 too}.
151
152
153%\item[Axis 3 \& 5] \textit{Robotique et contr\^{o}le/commande} and \textit{S\'{e}curit\'{e} et suret\'{e}} \\
154%VERS 1
155%Future control applications employ more and more SoC.
156%Application domains for such systems are for example the automotive domain, as well as the
157%aerospace and avionics domains.
158%In all cases, high performance and real time requirements are combined with
159%requirements to low power, low temperature, high dependability, and low cost.\\
160%Similary manufacturing, security and safety technologies require also more and more
161%computation power.
162%VERS 2 pour gagner de la place
163%Manufacturing, controling, security and safety technologies employ more and more SoC.
164%COACH will permit to design such complex digital systems.
165%\textbf{Thereby COACH indirectly answers to axis 3 and 5 too}.
166
167%\end{description}
168
169\item [Axis 3] \textit {Robotique et contr\^{o}le/commande}:
170
171COACH will address robotic and control applications by
172allowing to design complex systems based on MPSoC architecture.
173Like in the consumer electronics domain, future control applications
174will employ more and more SoC for safety and security applications.
175Application domains for such systems are for example automotive
176or avionics domains (e.g. collision-detection, intelligent navigation...).
177Manufacturing technology will also increasingly need high-end vision analysis and high-speed
178robot control.
179\textbf{Thereby COACH indirectly answers to axis 3}.
180
181\item [Axis 5] \textit {S\'{e}curit\'{e} et suret\'{e}}:
182
183The results of the COACH project will help users to build cryptographic secure systems implemented in
184hardware or both in software/hardware in an effective way, substantially enhancing the
185process productivity of the cryptographic algorithms hardware synthesis, improving the
186quality and reducing the design time and the cost of synthesised cryptographic devices.
187\textbf{Thereby COACH indirectly answers to axis 5}.
188
189\end{description}
190
191% IA2PC: 1) je ne vois pas trop ce que ca fait la.
192% IA2PC: 2) c'est deja dans le 2.1 pour le small business.
193% IA2PC: 3) Pour le large business, on avait mis ca dans la premiere version et je pense
194% IA2PC     toujours que le large business est encore vise par COACH.
195% IA2PC     Alain a enleve toute reference sur ce large business. Sa raison est +
196% IA2PC     politico/stylistique: en parlant des 2 on n'est pas tres clair et on brouille
197% IA2PC     le message. Je partage assez son avis, la version actuelle est + claire que
198% IA2PC     celle d'avant. De plus on ne dit jamais que l'on ne vise pas les grosses
199% IA2PC     boites.
200% IA2PC
201% IA2PC Bref je serai assez pour enlever ce paragraphe, et ne pas faire reference au large
202% IA2PC business meme dans les section precedente. Par contre d'essayer de recaser le reste dans
203% IA2PC les sections precedentes.
204%
205% VERS 2 pour gagner de la place je l'enleve
206
207%PC2IA ok pas de probleme
208
209% COACH technologies can be used in both large and small business, as they will permit users to design
210% embedded systems which meet a wide range of requirements: from low cost and low power consuming
211% devices to very high speed devices, based on parallel computing. For enterprises that will use embedded
212% systems designed via the approaches and tools targeted by COACH, there is the potential for greater
213% efficiency, improved business processes and models. The net results: lower costs, faster response times,
214% better service, and higher revenue.
215%\parlf
216Finally, it is worth to note that this project covers priorities defined by the commission
217experts in the field of Information Technolgies Society (IST) for Embedded
218Systems: \textit{ $<<$Concepts, methods and tools for designing systems dealing with systems complexity
219and allowing to apply efficiently applications and various products on embedded platforms,
220considering resources constraints (delays, power, memory, etc.), security and quality
221services$>>$}.
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