Changeset 248 for anr/section-2.2.tex
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- Feb 17, 2010, 2:56:27 PM (14 years ago)
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anr/section-2.2.tex
r247 r248 14 14 %%% 15 15 \parlf 16 COACH will contribute to build an open de velopmentand run-time16 COACH will contribute to build an open design and run-time 17 17 environment, including communication middleware and tools to support 18 18 developers in the production of embedded software, through all phases of the software lifecycle, … … 22 22 \item High level methods and concepts (esp. requirements and architectural level) for system 23 23 design, development and integration, addressing complexity aspects and modularity. 24 \item Open and modular de velopmentenvironments, enabling flexibility and extensibility by24 \item Open and modular design environments, enabling flexibility and extensibility by 25 25 means of new or sector-specific tools and ensuring consistency and traceability along the 26 26 development lifecycle. … … 29 29 \end{itemize} 30 30 COACH outcome will contribute to strengthen Europe's competitive position by developing 31 technologies and methodologies for product de velopment, focusing (in compliance with the31 technologies and methodologies for product design, focusing (in compliance with the 32 32 %scope of the above program) on technologies, engineering methodologies, novel tools, 33 33 %methods which facilitate resource use efficiency. The approaches and tools to be developed … … 75 75 % The TSAR MEDEA+ project (2008-2010) targets the design of a 76 76 scalable, coherent shared memory, multi-cores processor architecture, and uses the SoCLib 77 plaform for virtual prototyping. The COACH projectwill benefit from the synthesizable VHDL77 plaform for virtual prototyping. COACH will benefit from the synthesizable VHDL 78 78 models developped in the framework of TSAR (MIPS32 processor core, and RING interconnect). 79 79 \item[BioWic] … … 134 134 \item[Axis 2] \textit{Infrastructures pour l'Internet, le calcul intensif ou les services} \\ 135 135 COACH will address High-Performance Computing (HPC) by helping designers to accelerate an 136 application running on a PC by migrating critical parts into a SoC implemented on an FPGA 137 plugged to the PC bus (through a communication link like PCI/X). COACH will reduce the designer 138 effort through the development of tools that translate high level language programs to FPGA 139 configurations. Moreover, Dynamic Partial Reconfiguration will be used for improving HPC performance 136 application running on a PC. 137 By providing tools that translate high level language programs to FPGA 138 configurations, COACH will allow to easily migrate critical parts into an FPGA plugged to the 139 PC bus (through a communication link like PCI/X). 140 Moreover, Dynamic Partial Reconfiguration will be used for improving HPC performance 140 141 as well as reducing the required area. 141 142 \textbf{Thereby COACH partially corresponds to axis 2}. … … 168 169 \item [Axis 3] \textit {Robotique et contr\^{o}le/commande}: 169 170 170 COACH will address robotic and control applications domainsby171 allowing to design complex digitalsystems based on MPSoC architecture.171 COACH will address robotic and control applications by 172 allowing to design complex systems based on MPSoC architecture. 172 173 Like in the consumer electronics domain, future control applications 173 174 will employ more and more SoC for safety and security applications. 174 Application domains for such systems are for example automotive ,175 aerospaceor avionics domains (e.g. collision-detection, intelligent navigation...).175 Application domains for such systems are for example automotive 176 or avionics domains (e.g. collision-detection, intelligent navigation...). 176 177 Manufacturing technology will also increasingly need high-end vision analysis and high-speed 177 178 robot control.
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