1 | |
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2 | % Relevance of the proposal |
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3 | |
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4 | The COACH proposal addresses directly the \emph{Embedded Systems} item of |
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5 | the ARPEGE program. It aims to propose solutions to the societal/economical challenges by |
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6 | providing SMEs novel design capabilities enabling them to increase their |
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7 | design productivity with design exploration and synthesis methods that are placed on top |
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8 | of the state-of-the-art methods. |
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9 | This project proposes an open-source framework for mapping multi-tasks software applications |
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10 | on Field Programmable Gate Array circuits (FPGA). |
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11 | |
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12 | \par |
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13 | COACH will contribute to build an open development and run-time |
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14 | environment, including communication middleware and tools to support |
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15 | developers in the production of embedded software, through all phases of the software lifecycle, |
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16 | from requirements analysis until deployment and maintenance. |
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17 | |
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18 | More specifically, COACH focuses on: |
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19 | \begin{itemize} |
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20 | \item High level methods and concepts (esp. requirements and architectural level) for system |
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21 | design, development and integration, addressing complexity aspects and modularity. |
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22 | \item Open and modular development environments, enabling flexibility and extensibility by |
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23 | means of new or sector-specific tools and ensuring consistency and traceability along the |
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24 | development lifecycle. |
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25 | \item Light/agile methodologies and adaptive workflow providing a dynamic and adaptive |
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26 | environment, suitable for co-operative and distributed development. |
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27 | \end{itemize} |
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28 | |
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29 | COACH outcome will contribute to strengthen Europe's competitive position by developing |
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30 | technologies and methodologies for product development, focusing (in compliance with the |
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31 | scope of the above program) on technologies, engineering methodologies, novel tools, |
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32 | methods which facilitate resource use efficiency. The approaches and tools to be developed |
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33 | in COACH will enable new and emerging information technologies for the development, |
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34 | manufacturing and integration of devices and related software into end-products. |
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35 | |
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36 | \par |
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37 | The COACH project will benefit from a number of previous projects: |
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38 | \begin{itemize} |
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39 | \item SOCLIB : |
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40 | The SoCLib ANR platform (2007-2009) is an open infrastructure developped by 10 academic laboratories |
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41 | and 6 industrial companies. |
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42 | It supports system level virtual prototyping of shared memory, multi-processors |
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43 | architectures, and provides tools to map multi-tasks software application on these |
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44 | architectures, for reliable performance evaluation. |
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45 | The core of this platform is a library of SystemC simulation models for |
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46 | general purpose IP cores such as processors, buses, networks, memories, IO controller. |
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47 | The platform provides also embedded operating systems and software/hardware |
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48 | communication middleware. |
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49 | The synthesisable VHDL models of IPs are not part of the SoCLib platform, and |
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50 | this project enhances SoCLib by providing the synthesisable VHDL models required |
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51 | for FPGA synthesis. |
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52 | \item ROMA : |
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53 | The ROMA ANR project (2007-2009) involving IRISA, LIRMM, CEA List THOMSON France R\&D, proposes to develop a |
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54 | reconfigurable processor, exhibiting high silicon density and power efficiency, able to adapt its |
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55 | computing structure to computation patterns that can be speed-up and/or power efficient. |
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56 | The ROMA project study a pipeline-based of evolved low-power coarse grain reconfigurable |
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57 | operators to avoid traditional overhead, in reconfigurable devices, related to |
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58 | the interconnection network. |
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59 | The project will borrow from the ROMA ANR xxproject (2007-2009) and the ongoing |
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60 | joint INRIA-STMicro Nano2012 project to adapt existing pattern |
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61 | extraction algorithms and datapath merging techniques to the synthesis of customized |
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62 | ASIP processors. |
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63 | \item TSAR : |
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64 | The TSAR MEDEA+ project (2008-2010) involving BULL, THALES and the LIP6 targets the design of a |
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65 | scalable, coherent shared memory, multi-cores processor architecture, and uses the SoCLib |
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66 | plaform for virtual prototyping. The COACH project will benefit from the synthesizable VHDL |
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67 | models developped in the framework of TSAR (MIPS32 processor core, and RING interconnect). |
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68 | \item BioWic |
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69 | On the HPC application side, we also hope to benefit from the experience in |
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70 | hardware acceleration of bioinformatic algorithms/workfows gathered by the |
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71 | CAIRN group in the context of the ANR BioWic project (2009-2011), so as to |
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72 | be able to validate the framework on real-life HPC applications. |
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73 | \end{itemize} |
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74 | |
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75 | |
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76 | \par |
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77 | The laboratories involved in the COACH project have a well estabished expertise |
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78 | in the following domains: |
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79 | \begin{itemize} |
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80 | \item |
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81 | In the field of High Level Synthesis (HLS), the project |
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82 | leverages on know-how acquired over the last 15 years with the GAUT~\cite{gaut08} project |
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83 | developped by the Lab-STIC laboratory, and with the UGH~\cite{ugh08} project developped |
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84 | by the LIP6 and TIMA laboratories. |
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85 | \item |
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86 | Regarding system level architecture, the project is based on the know-how |
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87 | acquired by the LIP6 and TIMA laboratories in the framework of various projects |
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88 | (COSY \cite{disydent}, or MEDEA MESA \cite{dspin}), in the field of communication |
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89 | architectures for shared memory multi-processors systems. |
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90 | As an example, the DSPIN network on chip, is now used by BULL in the TSAR project. |
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91 | \item |
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92 | Regarding Application Specific Instruction Processor (ASIP) design, the |
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93 | CAIRN group at INRIA Bretagne Atlantique benefits from several years of |
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94 | expertise in the domain of retargetable compiler |
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95 | (Armor/Calife\cite{CODES99} since 1996, and the Gecos |
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96 | compilers\cite{ASAP05} since 2002). |
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97 | \item |
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98 | In the field of compilers, the Compsys group was founded in 2002 |
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99 | by several senior researchers with experience in |
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100 | high performance computing and automatic parallelization. They have been |
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101 | among the initiators of the polyhedral model, a theory which serve to |
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102 | unify many parallelism detection and exploitation techniques for regular |
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103 | programs. It is expected that the techniques developped by Compsys for |
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104 | parallelism detection, scheduling, process construction and memory management |
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105 | will be very useful as a Rfront end for the a high-level synthesis tools. |
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106 | \end{itemize} |
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107 | |
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108 | |
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109 | \par |
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110 | % FIXME A VERIFIER L'appel d'offre |
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111 | Finally, it is worth to note that this project cover priorities defined by the commission |
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112 | experts in the field of Information Technolgies Society (IST) for Embedded |
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113 | Systems: $<<$Concepts, methods and tools for designing systems dealing with systems complexity |
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114 | and allowing to apply efficiently applications and various products on embedded platforms, |
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115 | considering resources constraints (delais, power, memory, etc.), security and quality |
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116 | services$>>$. |
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117 | |
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118 | |
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