Changeset 97 for anr/section-2.2.tex


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Timestamp:
Feb 5, 2010, 10:16:22 PM (15 years ago)
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alain
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Alain : refonte de la section 2

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  • anr/section-2.2.tex

    r94 r97  
    22% Relevance of the proposal
    33
    4 The COACH proposal addresses directly the Embedded Systems of
     4The COACH proposal addresses directly the \emph{Embedded Systems} item of
    55the ARPEGE program. It aims to propose solutions to the societal/economical challenges by
    6 providing the industry the novel design capabilities enabling them to increase their
     6providing SMEs novel design capabilities enabling them to increase their
    77design productivity with design exploration and synthesis methods that are placed on top
    8 of the state-of-the-art methods, and thus, allowing the industry to better cope with the
    9 complexity of designed digital systems.
     8of the state-of-the-art methods.
     9This project proposes an open-source framework for mapping multi-tasks software applications
     10on Field Programmable Gate Array circuits (FPGA).
     11
    1012\par
    11 COACH will also contribute to the following strategic objectives of the ARPEGE program:
    12 COACH will specifically contribute to enable the building of open development and run-time
    13 environments for software and services, interoperable middleware and tools to support
     13COACH will contribute to build an open development and run-time
     14environment, including communication middleware and tools to support
    1415developers in the production of embedded software, through all phases of the software lifecycle,
    1516from requirements analysis until deployment and maintenance.
    16 \\
     17
    1718More specifically, COACH focuses on:
    1819\begin{itemize}
    … …  
    2526environment, suitable for co-operative and distributed development.
    2627\end{itemize}
     28
    2729COACH outcome will contribute to strengthen Europe's competitive position by developing
    2830technologies and methodologies for product development, focusing (in compliance with the
    … …  
    3133in COACH will enable new and emerging information technologies for the development,
    3234manufacturing and integration of devices and related software into end-products.
    33 \\
    34 This project proposes an open-source framework for architecture synthesis targeting
    35 Field Programmable Gate Array circuits (FPGA).
     35
    3636\par
    37 % LIEN AVEC AUTRES PROJETS: LIP6/TIMA OK
    38 To evaluate the different architectures, the project uses the prototyping platform of the SoCLIB ANR project (2006-2009).
    39 \\ % LIEN AVEC AUTRES PROJETS: IRISA
    40 The project will also borrow from the ROMA ANR project (2007-2009) and the ongoing
    41 joint INRIA-STMicro Nano2012 project. In particular we will adapt existing pattern
     37The COACH project will benefit from a number of previous projects:
     38\begin{itemize}
     39\item SOCLIB :
     40The SoCLib ANR platform (2007-2009) is an open infrastructure developped by 10 academic laboratories
     41and 6 industrial companies.
     42It supports system level virtual prototyping of shared memory, multi-processors
     43architectures, and provides tools to map multi-tasks software application on these
     44architectures, for reliable performance evaluation.
     45The core  of this platform is a library of SystemC simulation models for
     46general purpose IP cores such as processors, buses, networks, memories, IO controller.
     47The platform provides also embedded operating systems and software/hardware
     48communication middleware.
     49The synthesisable VHDL models of IPs are not part of the SoCLib platform, and
     50this project enhances SoCLib by providing the synthesisable VHDL models required
     51for FPGA synthesis.
     52\item ROMA :
     53The ROMA ANR project (2007-2009) involving IRISA, LIRMM, CEA List THOMSON France R\&D, proposes to develop a
     54reconfigurable processor, exhibiting high silicon density and power efficiency, able to adapt its
     55computing structure to computation patterns that can be speed-up and/or power efficient.
     56The ROMA project study a pipeline-based of evolved low-power coarse grain reconfigurable
     57operators to avoid traditional overhead, in reconfigurable devices, related to
     58the interconnection network.
     59The project will  borrow from the ROMA ANR xxproject (2007-2009) and the ongoing
     60joint INRIA-STMicro Nano2012 project to adapt existing pattern
    4261extraction algorithms and datapath merging techniques to the synthesis of customized
    4362ASIP processors.
    44 \par
     63\item TSAR :
     64The TSAR MEDEA+ project (2008-2010) involving BULL, THALES and the LIP6 targets the design of a
     65scalable, coherent shared memory, multi-cores processor architecture, and uses the SoCLib
     66plaform for virtual prototyping. The COACH project will benefit from the synthesizable VHDL
     67models developped in the framework of TSAR (MIPS32 processor core, and RING interconnect).
     68\item BioWic
    4569On the HPC application side, we also hope to benefit from the experience in
    4670hardware acceleration of bioinformatic algorithms/workfows gathered by the
    4771CAIRN group in the context of the ANR BioWic project (2009-2011), so as to
    4872be able to validate the framework on real-life HPC applications.
     73\end{itemize}
     74
     75
    4976\par
    50 %%% EXPERTISE DANS DES DOMAINES: LIP6/TIMA/LAB-STIC OK
    51 Regarding the expertise in  High Level Synthesis (HLS), the project
    52 leverages on know-how acquired over 15 years with GAUT~\cite{gaut08} project
    53 developped in Lab-STIC laboratory and UGH~\cite{ugh08} project developped
    54 in LIP6 and TIMA laboratories. \\
    55 Regarding architecture synthesis skills, the project is based on a know-how
    56 acquired over 10 years with the COSY European project (1998-2000) and the
    57 DISYDENT~\cite{disydent05} project developped in LIP6.\\
    58 %%% EXPERTISE DANS DES DOMAINES: IRISA OK
     77The laboratories involved in the COACH project have a well estabished expertise
     78in the following domains:
     79\begin{itemize}
     80\item
     81In the field of High Level Synthesis (HLS), the project
     82leverages on know-how acquired over the last 15 years with the GAUT~\cite{gaut08} project
     83developped by the Lab-STIC laboratory, and with the UGH~\cite{ugh08} project developped
     84by the LIP6 and TIMA laboratories.
     85\item
     86Regarding system level architecture, the project is based on the know-how
     87acquired by the LIP6 and TIMA laboratories in the framework of various projects 
     88(COSY \cite{disydent}, or MEDEA MESA \cite{dspin}), in the field of communication
     89architectures for shared memory multi-processors systems.
     90As an example, the DSPIN network on chip, is now used by BULL in the TSAR project.
     91\item
    5992Regarding Application Specific Instruction Processor (ASIP) design, the
    6093CAIRN group at INRIA Bretagne Atlantique benefits from several years of
    … …  
    6295(Armor/Calife\cite{CODES99} since 1996, and the Gecos
    6396compilers\cite{ASAP05} since 2002).
    64 %%% EXPERTISE DANS DES DOMAINES: LIP OK
    65 Compsys was founded in 2002 by several senior researchers with experience in
     97\item
     98In the field of compilers, the Compsys group was founded in 2002
     99by several senior researchers with experience in
    66100high performance computing and automatic parallelization. They have been
    67101among the initiators of the polyhedral model, a theory which serve to
    … …  
    69103programs. It is expected that the techniques developped by Compsys for
    70104parallelism detection, scheduling, process construction and memory management
    71 will be very useful as a first step for a high-level synthesis tool.
     105will be very useful as a Rfront end for the a high-level synthesis tools.
     106\end{itemize}
     107
    72108
    73109\par
    74 %%% DESCRIPTION DES PROJETS ANR UTILISES: SOCLIB OK
    75 The SoCLIB ANR platform were developped by 11 laboratories and 6 companies. It allows to
    76 describe hardware architectures with shared memory space and to deploy software
    77 applications on them to evaluate their performance.
    78 The heart of this platform is a library containing simulation models (in SystemC)
    79 of hardware IP cores such as processors, buses, networks, memories, IO controller.
    80 The platform provides also embedded operating systems and software/hardware
    81 communication components useful to implement applications quickly.
    82 However, the synthesisable description of IPs have to be provided by users. \\
    83 This project enhances SoCLib by providing synthesisable VHDL of standard IPs.
    84 In addition, HLS tools such as UGH and GAUT allow to get automatically a synthesisable
    85 description of an IP (coprocessor) from a sequential algorithm.
    86 \par
    87 
    88 %In multimedia applications, image processing is the major challenge embedded systems
    89 %have to face.  It is computationally intensive with power requirements to meet. Image
    90 %processing at pixel level, like image filtering, edge detection, pixel correlation or at
    91 %bloc level such as motion estimation have to be accelerated. For that goal,
    92 
    93 The ROMA project involving IRISA, LIRMM, CEA List THOMSON France R\&D, proposes to develop a
    94 reconfigurable processor, exhibiting high silicon density and power efficiency, able to adapt its
    95 computing structure to computation patterns that can be speed-up and/or power efficient.
    96 On the contrary of previous attempts  to design reconfigurable processors, which have
    97 focused on the definition of complex interconnection network between simple operators,
    98 the ROMA project study a pipeline-based of evolved low-power coarse grain reconfigurable
    99 operators to avoid traditional overhead, in reconfigurable devices, related to
    100 the interconnection network.
    101 %%% DESCRIPTION DES PROJETS ANR UTILISES: ROMA FIXME:IRISA (~10 lignes)
    102 %%% 2 IRISA ?
    103 %%% 2 ASIP tool such as ...
    104 %%% 2 ...
    105 %%% 2 Coach uses pattern extractions from ROMA
    106 \mustbecompleted{ROMA \\...\\...\\...\\...\\...\\...\\...\\IRISA (SD)\\}
    107 \par
    108110% FIXME A VERIFIER L'appel d'offre
    109 The different points proposed in this project cover priorities defined by the commission
     111Finally, it is worth to note that this project cover priorities defined by the commission
    110112experts in the field of Information Technolgies Society (IST) for Embedded
    111 systems: $<<$Concepts, methods and tools for designing systems dealing with systems complexity
     113Systems: $<<$Concepts, methods and tools for designing systems dealing with systems complexity
    112114and allowing to apply efficiently applications and various products on embedded platforms,
    113115considering resources constraints (delais, power, memory, etc.), security and quality
    114116services$>>$.
    115 \\
    116 Our team aims at covering all the steps of the design flow of architecture synthesis.
    117 Our project overcomes the complexity of using various synthesis tools and description
    118 languages required today to design architectures.
    119117
     118
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