[25] | 1 | The emerging complex and integrated heterogeneous embedded system platforms require |
---|
| 2 | adequate design methods able to efficiently model, explore, analyze and design the ever complex SW |
---|
| 3 | and HW architectures. Future Embedded Systems suppliers, in order to meet rapidly increasing |
---|
| 4 | performance requirements linked with a pressure to lower development cost and shorten time-tomarket, |
---|
| 5 | will have to adopt new design methods and flows able to keep pace with the increasing |
---|
| 6 | complexity of design problems. Such methods, addressing these challenges starting from high levels of |
---|
| 7 | abstraction, will have to perform large solution space exploration jointly for SW and HW (possibly |
---|
| 8 | reconfigurable), involving almost marginal design effort and offering a high predictability of results |
---|
| 9 | with respect to cost- and performance-functions. |
---|
| 10 | Current design methodologies provide quite low-level abstraction capabilities. However in a few years |
---|
| 11 | from now tens of programmable processors will be embedded in an IC with together over 100M |
---|
| 12 | transistors adding to the complexity of the problem of architecting such systems. Taking into account |
---|
| 13 | that the complexity of the SW part is pacing up at an even faster speed, current solutions to perform |
---|
| 14 | design space exploration, mainly manually based, by no means do supply a performance of adequate |
---|
| 15 | sufficiency. |
---|
| 16 | Consequently, there is an urgent need to leverage system level |
---|
| 17 | exploration through the use of a high level specification of the application and an early design |
---|
| 18 | space exploration steps. The first system oriented approaches are appearing, among which those |
---|
| 19 | based on C/C++ and SystemC are most popular. Such approaches can take place before and/or after |
---|
| 20 | the co-design or architecture refinement steps and targets the design space pruning in order to fully |
---|
| 21 | exploit potential solutions that meet design and application constraints (power, latency, |
---|
| 22 | throughput) within the design and market timeframe. |
---|
[17] | 23 | \\ |
---|
[25] | 24 | Thus, new system-level design flows need to be developed, enabling the exploration of an application |
---|
| 25 | independently of the implementation, this almost at the beginning of the design process. A |
---|
| 26 | fundamental element of this evolution is the definition of abstraction layers that should allow the |
---|
| 27 | systematic re-use of SW and HW components at the system level driven by performance estimation |
---|
| 28 | and analysis. It is the context in which the COACH modeling and estimation methods combined with |
---|
| 29 | compilers and design space exploration techniques. This approach will cause a real breakthrough in |
---|
| 30 | the embedded system design methodology, i.e. one of the radical innovations. |
---|
| 31 | \\ |
---|
| 32 | The reason is that COACH precedes the use of high-level design tools in the embedded |
---|
| 33 | systems design flows. In that way, it will make possible a real and efficiently combined |
---|
| 34 | exploitation of high-level synthesis tools, parallelising approaches and compilers, already |
---|
| 35 | available on the market. These tools and approaches are not yet massively adopted, precisely |
---|
| 36 | because this decisive design step is missing. COACH will indeed permit (i) to predict and |
---|
| 37 | control implementation optimizations, (ii) to target multiple implementation technologies |
---|
| 38 | (and thus the associated tools) from a unique specification and (iii) to efficiently integrate high |
---|
| 39 | and low-level design tools in a unique seamless design flow. |
---|
| 40 | \\ |
---|
| 41 | The performance estimation methods combined with the design space exploration techniques will |
---|
| 42 | finally allow the design process to start from system level specification and automatically explore the |
---|
| 43 | potential architectures in order to find out the optimal implementation in a shorter design time and at |
---|
| 44 | a lower global cost. |
---|
[17] | 45 | \par |
---|
| 46 | To get an efficient embedded system, designer has to take into account |
---|
| 47 | application characteristics when it chooses one of the former technologies. |
---|
| 48 | This choice is not easy and in most cases designer has to try different |
---|
| 49 | technologies to retain the most adapted one. |
---|
| 50 | \\ |
---|
| 51 | The first objective of COACH is to provide an open-source framework to |
---|
| 52 | design embedded system on FPGA device. |
---|
| 53 | COACH framework allows designer to explore various software/hardware |
---|
| 54 | partitions of the target application, to run timing and functional |
---|
| 55 | simulations and to generate automatically both the software and the |
---|
| 56 | synthesizable description of the hardware. |
---|
| 57 | The main topics of the project are: |
---|
| 58 | \begin{itemize} |
---|
| 59 | \item |
---|
| 60 | Design space exploration: It consists in analysing the application runnig |
---|
| 61 | on FPGA, defining the target technology (SoC, MPSoC, ASIP, ...) and |
---|
| 62 | hardware/software partitioning of tasks depending on technology choice. |
---|
| 63 | This exploration is driven basically by throughput, latency and power |
---|
| 64 | consumption criteria. |
---|
| 65 | \item |
---|
| 66 | Micro-architectural exploration: When hardware components are required, the |
---|
| 67 | HLS tools of the framework generate them automatically. At this stage the |
---|
| 68 | framework provides various HLS tools allowing the micro-architectural space |
---|
[30] | 69 | design exploration. The exploration criteria also are throughput, latency |
---|
[17] | 70 | and power consumption. |
---|
[30] | 71 | At this stage, preliminary source-level transformations will be |
---|
| 72 | required to improve the efficiency of the target component. |
---|
| 73 | For instance, one may transform a loop nest to expose parallelism, |
---|
| 74 | or shrink an array to promote it to a register or reduce a memory footprint. |
---|
| 75 | |
---|
[17] | 76 | \item |
---|
| 77 | Performance measurement: For each point of design space exploration, |
---|
| 78 | metrics of criteria are available such as throughput, latency, power |
---|
| 79 | consumption, area, memory allocation and data locality. They are evaluated |
---|
| 80 | using virtual prototyping, estimation or analysing methodologies. |
---|
| 81 | \item |
---|
| 82 | Targeted hardware technology: The COACH description of system is |
---|
| 83 | independent of the FPGA family. Every point of the design exploration |
---|
| 84 | space can be implemented on any FPGA having the required resources. |
---|
| 85 | Basically, COACH handles both Altera and Xilinx FPGA families. |
---|
| 86 | \end{itemize} |
---|
| 87 | As an extension of embedded system design, COACH deals also with High |
---|
| 88 | Performance Computing (HPC). |
---|
| 89 | In HPC, the kind of targeted application is an existing one running on PC. |
---|
| 90 | COACH helps designer to accelerate it by migrating critical parts into a |
---|
| 91 | SoC implemented on a FPGA plugged to the PC bus. |
---|
| 92 | \par |
---|
| 93 | COACH is the result of the will of several laboratory to unify their know |
---|
| 94 | how and skills in the following domains: Operating system and hardware |
---|
| 95 | communication (TIMA, SITI), SoC and MPSoC (LIP6 and TIMA), ASIP (IRISA) and |
---|
| 96 | HLS (LIP6, Lab-STIC and LIP). |
---|
| 97 | The project objective is to integrate these various domains into a unique |
---|
| 98 | free framework (licence ...) masking as much as possible these domains and |
---|
| 99 | its different tools to the user. |
---|
| 100 | |
---|