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1The emerging complex and integrated heterogeneous embedded system platforms require
2adequate design methods  to efficiently model, explore, analyze and design the ever complex software
3and hardware architectures. Future Embedded Systems suppliers, in order to meet rapidly increasing
4performance requirements and a pressure to lower development cost and shorten time-to-market,
5will have to adopt new design methods and flows in order to keep pace with the increasing
6complexity of design problems. Such methods, addressing these challenges starting from high levels of
7abstraction, will have to perform large solution space explorations both for software and (possibly
8reconfigurable) hardware, reducing the design effort and offering a high predictability of results
9with respect to cost and performance objectives.
10Current design methodologies provide quite low-level abstraction capabilities. However in a few years
11from now tens of programmable processors will be embedded in an IC with more than 100M
12transistors, therefore adding to the complexity of the problem of designing such systems.
13Taking into account that the complexity of the software part is increasing at an even
14faster rate, current solutions for design space exploration, mainly manually based, by no
15means do supply an adequate efficiency.
16Consequently, there is an urgent need to leverage system level
17exploration through the use of a high level specification of the application and an early design
18space exploration step. The first system oriented approaches are appearing, among which those
19based on C/C++ and SystemC are the most popular. Such approaches can take place before and/or after
20the co-design or architecture refinement steps and target the design space pruning in order to fully
21exploit potential solutions that meet design and application constraints (power, latency,
22throughput) within the design and market timeframe.
23\\
24Thus, new system-level design flows need to be developed, enabling the exploration of an application
25independently of the implementation, almost at the beginning of the design process.
26A fundamental element of this evolution is the definition of abstraction layers that should allow the
27performance driven re-use of software and hardware components at the system level.
28In this context, COACH will combine modeling and estimation methods and compilers and
29design space exploration techniques. This approach will be a radical innovation in
30embedded system design methodology.
31\\
32The reason is that the COACH framework is applied before high-level design tools in the embedded
33systems design flow. In that way, it will make possible a real and efficiently combined
34exploitation of high-level synthesis tools, parallelizing approaches and compilers, already
35available on the market. These tools and approaches are not yet massively adopted, precisely
36because this preliminary design step is missing. COACH will indeed permit (i) to predict and
37control implementation optimizations, (ii) to target multiple implementation technologies
38(and thus the associated tools) from a unique specification and (iii) to efficiently integrate high
39and low-level design tools in a unique seamless design flow.
40\\
41The performance estimation methods combined with the design space exploration techniques will
42finally allow the design process to start from system level specification and automatically explore the
43potential architectures in order to find out the optimal implementation in a shorter design time and at
44a lower global cost.
45\par
46To get an efficient embedded system, the system designer has to take into account
47application characteristics when it chooses one of the available technologies.
48This choice is not easy and in most cases the designer has to try different
49technologies to retain the most adapted one.
50\\
51The first objective of COACH is to provide an open-source framework to
52design embedded system on FPGA devices.
53The COACH framework allows the designer to explore various software/hardware
54partitions of the target application, to run timing and functional
55simulations and to generate automatically both the software and the
56synthesizable description of the hardware.
57The main topics of the project are:
58\begin{itemize} 
59\item
60\textbf{Design space exploration}: It consists in analysing the application runnig
61on FPGA, defining the target technology (SoC, MPSoC, ASIP, ...) and
62hardware/software partitioning of tasks depending on technology choice.
63This exploration is driven basically by throughput, latency and power
64consumption criteria.
65\item
66\textbf{Micro-architectural exploration}: When hardware components are required, the
67HLS tools of the framework generate them automatically. At this stage the
68framework provides various HLS tools that allow the micro-architectural space
69design exploration. The exploration criteria also are throughput, latency
70and power consumption.
71At this stage, preliminary source-level transformations will be
72required to improve the efficiency of the target component.
73For instance, one may transform a loop nest to expose parallelism,
74or shrink an array to promote it to a register or reduce a memory footprint.
75
76\item
77\textbf{Performance measurement}: For each point in the design space,
78figures of merit are available such as throughput, latency, power
79consumption, area, memory allocation and data locality. They are evaluated
80using virtual prototyping, estimation or analyzing methodologies.
81\item
82\textbf{Targeted hardware technology}: The COACH description of a system is
83independent of the FPGA family.  Every point of the design
84space can be implemented on any FPGA having the required resources.
85Basically, COACH handles both Altera and Xilinx FPGA families.
86\end{itemize}
87As an extension of embedded system design, COACH deals also with High
88Performance Computing (HPC).
89In HPC, the kind of targeted application is an existing one running on a PC.
90The COACH framework helps designer to accelerate it by migrating critical parts into a
91SoC implemented on an FPGA plugged to the PC bus.
92\par
93COACH is the result of the will of several laboratories to unify their knowhow
94and skills in the following domains: Operating system and hardware
95communication (\tima, \upmc), SoC and MPSoC (\upmc and \tima), ASIP (\irisa) and
96HLS (\upmc, \ubs) and compilation (\irisa, \lip).
97The project objective is to integrate these various domains into a unique
98free framework (licence ...) masking as much as possible these domains and
99its different tools to the user.
100
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