Changeset 46 for anr/section-2.tex

Timestamp:

Jan 29, 2010, 12:03:56 AM (14 years ago)

Author:

coach

Message:

 

File:

• anr/section-2.tex (modified) (4 diffs)

anr/section-2.tex

@@ -58 +58 @@
 \begin{itemize} 
 \item
-Design space exploration: It consists in analysing the application runnig
+\textbf{Design space exploration}: It consists in analysing the application runnig
 on FPGA, defining the target technology (SoC, MPSoC, ASIP, ...) and
 hardware/software partitioning of tasks depending on technology choice.
@@ -64 +64 @@
 consumption criteria.
 \item
-Micro-architectural exploration: When hardware components are required, the
+\textbf{Micro-architectural exploration}: When hardware components are required, the
 HLS tools of the framework generate them automatically. At this stage the
 framework provides various HLS tools that allow the micro-architectural space
@@ -75 +75 @@
 
 \item
-Performance measurement: For each point in the design space,
+\textbf{Performance measurement}: For each point in the design space,
 figures of merit are available such as throughput, latency, power
 consumption, area, memory allocation and data locality. They are evaluated
 using virtual prototyping, estimation or analyzing methodologies.
 \item
-Targeted hardware technology: The COACH description of a system is
+\textbf{Targeted hardware technology}: The COACH description of a system is
 independent of the FPGA family.  Every point of the design
 space can be implemented on any FPGA having the required resources.
@@ -93 +93 @@
 COACH is the result of the will of several laboratories to unify their knowhow
 and skills in the following domains: Operating system and hardware
-communication (\tima, \citi), SoC and MPSoC (\upmc and \tima), ASIP (\irisa) and
+communication (\tima, \upmc), SoC and MPSoC (\upmc and \tima), ASIP (\irisa) and
 HLS (\upmc, \ubs) and compilation (\irisa, \lip).
 The project objective is to integrate these various domains into a unique