source: anr/section-3.2.tex @ 284

% les objectifs scientifiques/techniques du projet.
The design steps are presented figure~\ref{coach-flow}.
\ADDED{
The end-user input is
either a HPC application (an application running on a PC that must be accelarate),
or an embedded application (a standalone application),
or a  sub-system application of a larger design.
The figure shows that the design flow of embedded and sub-system applications does not differ
except in the generation step and that the design flow of HPC application just adds a
preliminary step.
}
\begin{figure}[hbtp]\leavevmode\center
  \includegraphics[width=1.0\linewidth]{flow2}
  \caption{\label{coach-flow} COACH design flow}
\end{figure}
\begin{description}
\item[HPC setup:] During this step, the user splits the application into 2 parts: the host application
which remains on the PC and the SoC application which is mapped on the FPGA. 
COACH will provide a complete simulation model of the whole system (PC+communication+FPGA-SoC) 
which will allow performance evaluation.
\item[SoC design:] In this phase, 
COACH will allow the user to obtain virtual prototypes for the SoC at different abstraction levels.
The user input will consist of a process network describing the coarse grain parallelism
of the application, an instance of an architectural template
and a mapping of processes on the architectural template components. 
COACH will offer different targets to map the processes:  
software (the process runs as a software task on a SoC processor),
ASIP (the process runs as a software task on a SoC processor enhanced with dedicated instructions),
and hardware (the process is implemented as a synthesized hardware coprocessor).
\begin{SUPPRESSEDENV}
\item[Application compilation:]
Once the SoC architecture is validated through performances analysis,
COACH will generate automatically an executable containing the host application and
the FPGA bitstream. This bitstream contains 
both the hardware architecture and the SoC application software.
The user will be able to launch the application by
loading the bitstream on an FPGA and running the executable on PC.
\end{SUPPRESSEDENV}\begin{ADDEDENV}
\item[Generation:]
Once the SoC architecture is validated through performances analysis,
COACH generates its bitstream in the case of HPC or embedded application,
or its IP-XACT description for its integration in the case of a sub-system application.
Both descriptions contain the hardware architecture and the application software.
Furthermore in the HPC case, an executable containing the host application is
also generated and the user will be able to launch the application by loading
the bitstream on an FPGA and running the executable on PC.
\end{ADDEDENV}
\end{description}
 
% l'avancee scientifique attendue. Preciser l'originalite et le caractere 
% ambitieux du projet. 
%FIXME == {NON ceci n'est pas une contribution scientifique. A re-ecrire}

%The main scientific contribution of the project is to unify various synthesis techniques
%(same input and output formats) allowing the user to swap without engineering effort
%from one to another and even to chain them. For instance, it will be possible to run loop transformations before synthesis.
%Another advantage of this framework is to provide different abstraction levels from
%a single description.
%Finally, this description is device family independent and its hardware implementation
%is automatically generated.

% Detailler les verrous scientifiques et techniques a lever par la realisation du projet.
Hardware/Software co-design is a very complex task. To simplify it, COACH will address the
following scientific and technological barriers:
\begin{description}
\item[\textit{Design Space Exploration by Virtual Prototyping}]:
    The COACH environment will allow to easily map a parallel application (formally described as
    an abstract network of process and communication channels)  
    COACH will permit the system designer to explore the design space, and to define the best 
    hardware/software partitioning of the application.
\item[\textit{Integration of system level modeling and HLS tools}]:
    COACH will support the automated generation of hardware accelerators when required
    by using High-Level Synthesis (HLS) tools. These HLS tools will be
    fully integrated into a complete system-level design environment.
    Moreover, COACH will support both data and control dominated applications,
    and the HLS tools of COACH will support a common language and coding style 
    to avoid re-engineering by the designer.
    COACH will provide a tool which will automatically explore the micro-architectural 
    design space of coprocessor.
\item[\textit{High-level code transformation}]:
    COACH will allow to optimize the memory usage, to enhance the parallelism through 
    loop transformations and parallelization. The challenge is to identify the coarse 
    grained parallelism and to generate,
    from a sequential algorithm, application containing multiple communicating
    tasks. COACH will adapt techniques which were developed in the 1990 for 
    the construction of distributed programs. However, in the context of HLS, there are 
    several original problems to be solved, related to the  FIFO communication channels and with 
    memory optimization. 
    COACH will support code transformation by providing a source to source C2C tool.
\item[\textit{Unified Hardware/Software communication middleware}]:
    COACH will rely on he SoCLib experience to implement an unified hardware/software communication 
    infrastructure and communication APIs (Application Programming Interface), to support  
    communications between software tasks running on embedded processors and dedicated 
    hardware coprocessors. The main issue here is to support easy migration 
    from a software implementation to an hardware implementation.
\item[\textit{Processor customization}]:
    ASIP (Application Specific Instruction Processor) design will be addressed by the COACH project. 
    COACH will allow system designers to explore the various level of interactions between 
    the original CPU micro-architecture and its extension. It will also allow to retarget 
    the compiler instruction-selection pass. Finally, COACH will integrate ASIP synthesis
    in a complete System-level design framework.
\end{description}

%Presenter les resultats escomptes en proposant si possible des criteres de reussite 
%et d'evaluation adaptes au type de projet, permettant d'evaluer les resultats en 
%fin de projet.
The main result is the framework. It is composed concretely of: 
a communication middleware for HPC, 
5 HAS tools (control dominated HLS, data dominated HLS, Coarse grained HLS, 
Memory optimization HLS and ASIP),
3 architectural templates that are synthesizable and that can be prototyped,
one design space exploration tool,
1 operating systems (DNA/OS).
\\
The framework functionalities will be demonstrated with the demonstrators
(see task-7 page~\pageref{task-7}) and the tutorial example (see task-8
page~\ref{subtask-tutorial}).