Changeset 280 for anr/section-3.2.tex


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Timestamp:
Nov 30, 2010, 6:11:33 PM (14 years ago)
Author:
coach
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Changed design flow figure and corresponding text.

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  • anr/section-3.2.tex

    r277 r280  
    55either a HPC application (an application running on a PC that must be accelarate),
    66or an embedded application (a standalone application),
    7 or a sub-system application of a larger design.}
     7or a  sub-system application of a larger design.
     8The figure shows that the design flow of embedded and sub-system applications does not differ
     9except in the generation step and that the design flow of HPC application just adds a
     10preliminary step.
     11}
    812\begin{figure}[hbtp]\leavevmode\center
    9   \includegraphics[width=.8\linewidth]{flow}
     13  \includegraphics[width=1.0\linewidth]{flow2}
    1014  \caption{\label{coach-flow} COACH design flow}
    1115\end{figure}
     
    2428ASIP (the process runs as a software task on a SoC processor enhanced with dedicated instructions),
    2529and hardware (the process is implemented as a synthesized hardware coprocessor).
     30\begin{SUPPRESSEDENV}
    2631\item[Application compilation:]
    27 \begin{SUPPRESSEDENV}
    2832Once the SoC architecture is validated through performances analysis,
    2933COACH will generate automatically an executable containing the host application and
     
    3337loading the bitstream on an FPGA and running the executable on PC.
    3438\end{SUPPRESSEDENV}\begin{ADDEDENV}
     39\item[Generation:]
    3540Once the SoC architecture is validated through performances analysis,
    3641COACH generates its bitstream in the case of HPC or embedded application,
     
    6065\begin{description}
    6166\item[\textit{Design Space Exploration by Virtual Prototyping}]:
    62         The COACH environment will allow to easily map a parallel application (formally described as
    63         an abstract network of process and communication channels) 
    64         COACH will permit the system designer to explore the design space, and to define the best
    65         hardware/software partitioning of the application.
     67    The COACH environment will allow to easily map a parallel application (formally described as
     68    an abstract network of process and communication channels) 
     69    COACH will permit the system designer to explore the design space, and to define the best
     70    hardware/software partitioning of the application.
    6671\item[\textit{Integration of system level modeling and HLS tools}]:
    67         COACH will support the automated generation of hardware accelerators when required
    68         by using High-Level Synthesis (HLS) tools. These HLS tools will be
    69         fully integrated into a complete system-level design environment.
    70         Moreover, COACH will support both data and control dominated applications,
    71         and the HLS tools of COACH will support a common language and coding style
    72         to avoid re-engineering by the designer.
    73         COACH will provide a tool which will automatically explore the micro-architectural
    74         design space of coprocessor.
     72    COACH will support the automated generation of hardware accelerators when required
     73    by using High-Level Synthesis (HLS) tools. These HLS tools will be
     74    fully integrated into a complete system-level design environment.
     75    Moreover, COACH will support both data and control dominated applications,
     76    and the HLS tools of COACH will support a common language and coding style
     77    to avoid re-engineering by the designer.
     78    COACH will provide a tool which will automatically explore the micro-architectural
     79    design space of coprocessor.
    7580\item[\textit{High-level code transformation}]:
    76         COACH will allow to optimize the memory usage, to enhance the parallelism through
    77         loop transformations and parallelization. The challenge is to identify the coarse
    78         grained parallelism and to generate,
    79         from a sequential algorithm, application containing multiple communicating
    80         tasks. COACH will adapt techniques which were developed in the 1990 for
    81         the construction of distributed programs. However, in the context of HLS, there are
    82         several original problems to be solved, related to the  FIFO communication channels and with
    83         memory optimization.
    84         COACH will support code transformation by providing a source to source C2C tool.
     81    COACH will allow to optimize the memory usage, to enhance the parallelism through
     82    loop transformations and parallelization. The challenge is to identify the coarse
     83    grained parallelism and to generate,
     84    from a sequential algorithm, application containing multiple communicating
     85    tasks. COACH will adapt techniques which were developed in the 1990 for
     86    the construction of distributed programs. However, in the context of HLS, there are
     87    several original problems to be solved, related to the  FIFO communication channels and with
     88    memory optimization.
     89    COACH will support code transformation by providing a source to source C2C tool.
    8590\item[\textit{Unified Hardware/Software communication middleware}]:
    86         COACH will rely on he SoCLib experience to implement an unified hardware/software communication
    87         infrastructure and communication APIs (Application Programming Interface), to support 
    88         communications between software tasks running on embedded processors and dedicated
    89         hardware coprocessors. The main issue here is to support easy migration
    90         from a software implementation to an hardware implementation.
     91    COACH will rely on he SoCLib experience to implement an unified hardware/software communication
     92    infrastructure and communication APIs (Application Programming Interface), to support 
     93    communications between software tasks running on embedded processors and dedicated
     94    hardware coprocessors. The main issue here is to support easy migration
     95    from a software implementation to an hardware implementation.
    9196\item[\textit{Processor customization}]:
    92         ASIP (Application Specific Instruction Processor) design will be addressed by the COACH project.
    93         COACH will allow system designers to explore the various level of interactions between
    94         the original CPU micro-architecture and its extension. It will also allow to retarget
    95         the compiler instruction-selection pass. Finally, COACH will integrate ASIP synthesis
    96         in a complete System-level design framework.
     97    ASIP (Application Specific Instruction Processor) design will be addressed by the COACH project.
     98    COACH will allow system designers to explore the various level of interactions between
     99    the original CPU micro-architecture and its extension. It will also allow to retarget
     100    the compiler instruction-selection pass. Finally, COACH will integrate ASIP synthesis
     101    in a complete System-level design framework.
    97102\end{description}
    98103
     
    103108a communication middleware for HPC,
    1041095 HAS tools (control dominated HLS, data dominated HLS, Coarse grained HLS,
    105 Memory optimisation HLS and ASIP),
     110Memory optimization HLS and ASIP),
    1061113 architectural templates that are synthesizable and that can be prototyped,
    107112one design space exploration tool,
    108 2 operating systems (DNA/OS and MUTEKH).
     1131 operating systems (DNA/OS).
    109114\\
    110 The framework fonctionality will be demonstrated with the demonstrators
     115The framework functionalities will be demonstrated with the demonstrators
    111116(see task-7 page~\pageref{task-7}) and the tutorial example (see task-8
    112117page~\ref{subtask-tutorial}).
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