source: anr/section-4.4.tex @ 40

\begin{figure}\leavevmode\center
\definecolor{gtcBoxHeavy}{rgb}{0.10,0.10,0.90}
\definecolor{gtcBoxLight}{rgb}{0.9,0.90,0.99}
\definecolor{gtcTaskBG0} {rgb}{0.99,0.90,0.7}
\definecolor{gtcTaskBG1} {rgb}{0.90,0.99,0.7}
\definecolor{gtcMilestone}{rgb}{0.9,0.4,0.4}
\immediate\write\ganttdata{ML=6 ML=12 ML=18 ML=24}
\def\ganttlabelstyle#1{\begin{small}#1\end{small}}
\def\gantttitlestyle#1{\begin{scriptsize}\textit{#1}\end{scriptsize}}
\hspace*{-.6cm}
\input{gantt.tex}
\caption{\label{gantt}Gantt diagram of delivrables}
\end{figure}

The figure~\ref{gantt} presents the Gantt diagram of the project.
Before the final release (T0+36), there are 4 milestones (red lines on the figure) at
$T0+6$, $T0+12$, $T0+18$ and $T0+24$  that are rendez-vous points of the precedent
delivrables.
\begin{description}
\item[Milestone 1 ($T0+6$)] Specification of COACH inputs, of the \xcoach format and of
    demonstatrors as a reference software.
\item[Milestone 2 ($T0+12$)] The first COACH release. At this step the demonstrators are
    written in the COACH input format. This COACH release allows to prototype and to generate the FPGA-SoC.
    The main restrictions are:
    1) only the COACH architectural template is supported,
    2) HAS is not available (but prototyping with virtual coprocessors is available),
    3) Enhanced communication schemes are not available.
\item[Milestone 3 ($T0+18$)]  The second COACH release. At this step most of the COACH
    features are availables.
    The main restriction is that COACH can not yet generate FPGA-SoC for ALTERA and XILINX
    architectural templates.
    The others restriction is that the HAS tools are not yet fully operational.
\item[Milestone 4 ($T0+24$)] The pre-release of the COACH project. The full design flow is
    supported.
    The main restriction are:
    1) The HAS tools are not yet optimum,
    2) dynamic reconfiguration is not supported,
    3) \mustbecompleted{FIXME:ALL .....}
\item[Final Release ($T0+36$)]
\end{description}
This organisation allows to advance globally the project step by step mixing development
and demonstrator delivrables.
Hence, demonstrator feed-back will arrive early and so the risk to point out incompatibility
at the integration phase is significantly reduced.
\par
The project has several critical issues:
\begin{description}
\item[\xcoachplus format (\novers{\specXcoachDoc}, \novers{\specXcoachToC})]
    Because all the HAS tools rely on it, it is a
    crucial task. There are no work-arround but as mentionned in
    section~\ref{xcoach-problem} (page~\pageref{xcoach-problem}) we have worked on it
        for a year and are confident.
\item[\xcoachplus format (\novers{\specXcoachDoc},
      \novers{\specXcoachToSystemC}, \novers{\specXcoachToVhdl})]
    Its aim is the generation of the coprocessors (hardware \& prototyping model).
    By centralizing the coprocessor generation, it guarantees their functioning
    independently of the used HAS tools.
        Our experience with UGH and GAUT give us confidence in the succes of this
        task.
\item[prototyping of ALTERA \& XILINX architectural templates ({\csgAlteraSystemC},
     {\csgXilinxSystemC}]
     The SocLib component library contains most of the SystemC models used for the
     prototyping description of the ALTERA and XILINX architectural templates.
     Nevertheless, at this time we do not know how many are missing and if the existing
     are really useables.
     If the work of theses tasks is too important, they will be abandoned.
     In this case the work-arround to prototype the XILINX and ALTERA architectural
     templates is to use the COACH one. These architectures being very similar, the
     simulation results must be proportional. Theses tasks will be changed by measuring
     the deviance.
\item[VCI/AVALON \& VCI/PLB bridges (\novers{\hpcAvalonBridge}, \novers{\hpcPlbBridge})]
     If one of these tasks is impossible or too important or leads to inefficiency,
     it will be abandoned.
     In this case, the COACH architectural template will not be available for HPC and
     a SystemC VCI model corresponding to the PCI/X IP will be developped to allow
     prototyping.
\end{description}