[62] | 1 | \subsection{Dissemination} |
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| 2 | |
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[134] | 3 | The COACH project will bring new scientific results in various fields, such as high level synthesis, |
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[237] | 4 | hardware/software codesign, virtual prototyping, hardware oriented compilation techniques, |
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[196] | 5 | automatic parallelisation, etc. These results will be published in relevant International |
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[62] | 6 | Conferences, namely DATE, DAC, or ICCAD. |
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| 7 | |
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[134] | 8 | More generally, the COACH infrastructure and the design flow supported by the COACH |
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[62] | 9 | tools and libraries will be promoted by proposing tutorials on FPGA oriented system level synthesis |
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[196] | 10 | in various worshops and conferences (DATE, DAC, CODES+ISSS...). |
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[62] | 11 | |
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[196] | 12 | Several COACH partners being members of the HiPEAC European Network of Excellence |
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| 13 | (High Performance and Embedded Architecture and Compilation), courses will be proposed for the |
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| 14 | HiPEAC summer school on Advanced Computer Architecture and Compilation for Embedded Systems. |
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| 15 | |
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[62] | 16 | Following the general policy of the SoCLib platform, the COACH project will be an |
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[237] | 17 | open infrastructure, and the COACH tools and libraries will be available in the framework |
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[62] | 18 | of the SoCLib WEB server. This server will be maintened by the UPMC/LIP6 laboratory. |
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| 19 | |
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| 20 | \subsection{Exploitation of results} |
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| 21 | |
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[134] | 22 | The main goal of the COACH project is to help SMEs (Small and Medium Enterprises) |
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[62] | 23 | to enter the world of MPSoC technologies. For small companies, the cost is a primary concern. |
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| 24 | Moreover, these companies have not always in-home expertise in hardware design and VHDL modelling. |
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[134] | 25 | As the fabrication costs of an ASIC is generally too high for SMEs, the COACH project focus |
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[62] | 26 | on FPGA technologies. Regarding the design tools, the cost of advanced ESL (Electronic System Design) |
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[134] | 27 | tools is an issue, and the COACH project will follow the same general policy as the SoCLib platform : |
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[62] | 28 | |
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| 29 | \begin{itemize} |
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| 30 | \item |
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[134] | 31 | All software tools supporting the COACH design flow will be available as free software. |
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| 32 | All academic partners contributing to the COACH project agreed to distribute the ESL software |
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[62] | 33 | tools under the same GPL license as the SoCLib tools. |
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| 34 | \item |
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[119] | 35 | The SystemC simulation models for the hardware components |
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[62] | 36 | used by the SoCLib architectural template will be distributed as free software |
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| 37 | under a non-contaminant LGPL license. |
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| 38 | \item |
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| 39 | The synthesizable VHDL models supporting the neutral architectural template |
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| 40 | (corresponding to the SocLib IP cores library), will have two modes of dissemination. |
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| 41 | A typical MPSoC contains not only dedicated, synthesized coprocessors. It contains |
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| 42 | also general purpose, reusable components, such as processor cores, memory controllers |
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| 43 | optimised cache controllers, peripheral controllers, or bus controllers. |
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| 44 | For non commercial use (i.e. research or education in an academic context, |
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| 45 | or feasbility study in an industrial context), the synthesizable VHDL models will be freely available. |
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| 46 | For commercial use, commercial licenses will be negociated between the owners and the customers. |
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| 47 | \item |
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[134] | 48 | The proprietary \altera, \xilinx and \zied IP core libraries are commercial products |
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[62] | 49 | that are not involved by the free software policy, but these libraries will be supported by the |
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[134] | 50 | synthesis tools developped in the COACH project. |
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[62] | 51 | \end{itemize} |
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| 52 | |
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[150] | 53 | This general approach is supported by a large number (\letterOfInterestNb) of SMEs, as |
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| 54 | demonstrated by the "letters of interest" that have been collected during the preparation |
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| 55 | of the project and presented in annexe~\ref{lettre-soutien}. |
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[136] | 56 | |
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| 57 | \subsection{Indusrial Interest in COACH} |
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| 58 | |
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| 59 | \subsubsection*{Partner: \textit{\bull}} |
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| 60 | The team of \bull participating to the COACH project is from the Server Development |
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| 61 | Department who is in charge of developing hardware for open servers (e.g. NovaScale) and |
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| 62 | HPC solutions. The main expectation from COACH is to derive a new component (fine-grain |
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| 63 | FPGA parallelism) to add to existing Bull HPC solutions. |
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| 64 | |
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| 65 | \subsubsection*{Partner: \textit{\xilinx}} |
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| 66 | Computing power potential of our FPGA architectures |
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| 67 | growing very quickly on one side, and complexity of designs implemented |
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| 68 | using our FPGAs dramatically increasing on the other side, it is very |
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| 69 | interesting for us to get high level design methodologies progressing |
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| 70 | quickly and targetting our FPGAs in the most possible efficient way. |
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| 71 | \parlf |
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| 72 | \xilinx goal is to get COACH to generate bitstream optimized as much as possible for |
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| 73 | \xilinx FPGAs in order to both, validate the methodology on our FPGA families, and ease |
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| 74 | future work of our customers. |
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| 75 | |
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| 76 | \subsubsection*{Partner: \textit{\thales}} |
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| 77 | \noindent |
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| 78 | \thales has two main reasons to use the COACH platform: |
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[62] | 79 | \begin{itemize} |
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[136] | 80 | \item The huge increase of the complexity of the systems in particular by their |
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| 81 | heterogeneity, raises the issues of design cost and time in the same proportion. The |
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| 82 | divisions need a design tool which supports the implementation of the applications from |
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| 83 | algorithm description to the executable code on platforms composed of several general |
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| 84 | purpose processors and dedicated IPs. |
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| 85 | \item The applications are more and more complex and adaptable to the environment which |
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| 86 | leads to a mixture of control aspects and data stream computing aspects. A new approach |
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| 87 | is necessary to be able to describe this type of application and manage the high level |
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| 88 | synthesis of system embedding control and data flow aspects. |
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| 89 | \end{itemize} |
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| 90 | \parlf |
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| 91 | TRT (Thales Research and Technology) has the mission to assess and de-risk the emerging |
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| 92 | technologies in its domains of expertise. Specifically in COACH, the studied technology is |
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| 93 | a method and associated tools to make the bridge between application capture at system |
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| 94 | level and the implementation on heterogeneous distributed computing architectures. The |
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| 95 | main stake for Thales behind this is the future design process that will be applied to its |
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| 96 | system teams in the future for the computation-intensive sensor applications. In a context |
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| 97 | of very instable market of tools for parallel programming, it is important to experiment |
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| 98 | and demonstrate the candidate technologies. |
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| 99 | \\ |
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| 100 | In its role of internal dissemination, TRT will make the demonstration of the full design |
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| 101 | flow within Thales, and will keep available a platform to later evaluate additional |
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| 102 | applications coming from the Business Units. |
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| 103 | \\ |
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| 104 | The COACH platform will be used in the new \thales products in which the algorithms are more |
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| 105 | and more dependent of the environment and have to permanently adapt their behavior in |
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| 106 | varying environments. The target markets are the critical infrastructures security and |
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| 107 | border monitoring. |
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| 108 | |
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| 109 | \subsubsection*{Partner: \textit{\zied}} |
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| 110 | |
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| 111 | \zied is developing a new architecture for embedded system. Our interest in using COACH |
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| 112 | are: |
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| 113 | \begin{itemize} |
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| 114 | \item firstly, to validate our new architecture by emulating it with COACH. |
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| 115 | \item Secondly, to use this emulator and the COACH potential to quickly setup |
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| 116 | demonstrator to our customer. |
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| 117 | \end{itemize} |
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| 118 | |
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| 119 | \subsubsection*{Partner: \textit{\navtel}} |
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| 120 | \navtel has a platform for high performence computation based on ARM processor and FPGAs |
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| 121 | that embedde coprocessors. Currently, the coprocessors are handmade and their designs |
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| 122 | constitute an important part of our product cost. We have try free HLS tools to diminish |
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| 123 | them but the quality of the generated designs was not sufficient to be useable. |
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| 124 | So our interest in COACH is mainly the HLS tools. |
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| 125 | |
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| 126 | \subsubsection*{Industrial supports} |
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| 127 | The following SMEs demonstrate interest to the COACH project (see the "letters of |
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| 128 | interest" in annexe~\ref{lettre-soutien}) and will follow the COACH evolution and will |
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| 129 | evaluate it: |
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[150] | 130 | \letterOfInterest{ADACSYS}{lettres/Coach_ADACSYS_lettre_interet}, |
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| 131 | \letterOfInterest{MAGILLEM Design Services}{lettres/Coach_lettre_interet_MDS}, |
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[168] | 132 | \letterOfInterest{INPIXAL}{lettres/inpixal.jpg}, |
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| 133 | \letterOfInterest{CAMKA System}{lettres/CAMKA-System.pdf}. |
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[62] | 134 | |
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[150] | 135 | \letterOfInterestClose |
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| 136 | |
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[62] | 137 | \subsection{Management of Intellectual Property} |
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| 138 | A global consortium agreement will be defined during the first six monts of the project. |
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[134] | 139 | As already stated, the COACH project has been prepared during one year by a monthly meeting |
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[62] | 140 | involving the five academic partners. The general free software policy described in the |
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| 141 | previous section has been agreed by academic partners and has been |
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| 142 | approved by all industrial participants. This free software policy will |
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| 143 | simplify the definition of the consortium agreement. |
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| 144 | |
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