Changeset 283 for anr/section-5.tex

Timestamp:

Nov 30, 2010, 6:14:47 PM (14 years ago)

Author:

coach

Message:

Suppressed reference to Flexras and Navtel.

File:

• anr/section-5.tex (modified) (4 diffs)

anr/section-5.tex

@@ -43 +43 @@
 optimised cache controllers, peripheral controllers, or bus controllers.
 For non commercial use (i.e. research or education in an academic context,  
-or feasbility study in an industrial context), the synthesizable VHDL models will be freely available.
-For commercial use, commercial licenses will be negociated between the owners and the customers.
+or feasibility study in an industrial context), the synthesizable VHDL models will be freely available.
+For commercial use, commercial licenses will be negotiated between the owners and the customers.
 \item
-The proprietary \altera, \xilinx and \zied IP core libraries are commercial products
+The proprietary \altera and \xilinx IP core libraries are commercial products
 that are not involved by the free software policy, but these libraries will be supported by the 
-synthesis tools developped in the COACH project.
+synthesis tools developed in the COACH project.
 \end{itemize}
 
@@ -57 +57 @@
 \subsection{Indusrial Interest in COACH}
 
+\subsubsection*{Partner: \textit{\mds}}
+
+\mustbecompleted{Emanuel ....}
+
 \subsubsection*{Partner: \textit{\bull}}
 The team of \bull participating to the COACH project is from the Server Development
@@ -63 +67 @@
 FPGA parallelism) to add to existing Bull HPC solutions.
 
-\subsubsection*{Partner: \textit{\xilinx}}
-Computing power potential of our FPGA architectures
-growing very quickly on one side, and complexity of designs implemented
-using our FPGAs dramatically increasing on the other side, it is very
-interesting for us to get high level design methodologies progressing
-quickly and targetting our FPGAs in the most possible efficient way.
-\parlf
-\xilinx goal is to get COACH to generate bitstream optimized as much as possible for
-\xilinx FPGAs in order to both, validate the methodology on our FPGA families, and ease
-future work of our customers.
+%\subsubsection*{Partner: \textit{\xilinx}}
+%Computing power potential of our FPGA architectures
+%growing very quickly on one side, and complexity of designs implemented
+%using our FPGAs dramatically increasing on the other side, it is very
+%interesting for us to get high level design methodologies progressing
+%quickly and targetting our FPGAs in the most possible efficient way.
+%\parlf
+%\xilinx goal is to get COACH to generate bitstream optimized as much as possible for
+%\xilinx FPGAs in order to both, validate the methodology on our FPGA families, and ease
+%future work of our customers.
 
 \subsubsection*{Partner: \textit{\thales}}
@@ -107 +111 @@
 border monitoring.
 
-\subsubsection*{Partner: \textit{\zied}}
+\subsubsection*{Industrial supports}
 
-\zied is developing a new architecture for embedded system. Our interest in using COACH
-are:
-\begin{itemize}
-  \item firstly, to validate our new architecture by emulating it with COACH.
-  \item Secondly, to use this emulator and the COACH potential to quickly setup
-  demonstrator to our customer.
-\end{itemize}
-
-\subsubsection*{Partner: \textit{\navtel}}
-\navtel has a platform for high performence computation based on ARM processor and FPGAs
-that embedde coprocessors. Currently, the coprocessors are handmade and their designs
-constitute an important part of our product cost. We have try free HLS tools to diminish
-them but the quality of the generated designs was not sufficient to be useable.
-So our interest in COACH is mainly the HLS tools.
-
-\subsubsection*{Industrial supports}
+\mustbecompleted{NON A JOUR}
 The following SMEs demonstrate interest to the COACH project (see the "letters of
 interest" in annexe~\ref{lettre-soutien}) and will follow the COACH evolution and will