source: anr/section-6.1.tex @ 117

Last change on this file since 117 was 99, checked in by coach, 15 years ago

IA: 1) mise en page et verification de 2, 2.1, 2.2 4.1. 2) entrer bull/xilinx/navtel dans 6.1 3) xilinx dans 7.

File size: 12.0 KB
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1%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
2\subsubsection{\irisa}
3
4The CAIRN group is an INRIA - Bretagne Atlantique project and a part of IRISA, UMR
56074. CAIRN members are affiliated from University of Rennes\~1 or Ecole Normale
6Supérieure de Cachan. the goal of CAIRN is to study reconfigurable system-on-chip,
7i.e. hardware systems whose configuration may change before or even during execution.
8To this end, CAIRN intends to approach reconfigurable architectures from three angles:
9the invention of new reconfigurable platforms, the development of associated
10transformation, compilation and synthesis tools, and the exploration of the interaction
11between algorithms and architectures.
12
13%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
14\subsubsection{\lip}
15The Compsys group of Ecole Normale Sup\'erieure de Lyon is a project-team
16of INRIA Rh\^one-Alpes and a part of Laboratoire de l'Informatique du
17Parall\'elisme (LIP), UMR 5668 of CNRS. It has four permanent researchers
18and a variable number of PhD students and post-docs. Its field of
19expertise is compilation for embedded system, optimizing compilers
20and automatic parallelization. It  has authored or contributed to
21several well known libraries for linear programming, polyhedra manipulation
22and optimization in general. It has strong industrial cooperations, notably
23with ST Microelectonics and Thales.
24
25
26%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
27\subsubsection{\tima}
28The TIMA laboratory ("Techniques of Informatics and Microelectronics
29for integrated systems Architecture") is a public research laboratory
30sponsored by Centre National de la Recherche Scientifique (CNRS, UMR5159),
31Grenoble Institute of Technology (Grenoble-INP) and Universitᅵ Joseph Fourier
32(UJF).
33The research topics cover the specification, design, verification, test,
34CAD tools and design methods for integrated systems, from analog and
35digital components on one end of the spectrum, to multiprocessor
36Systems-on-Chip together with their basic operating system on the other end.
37
38Currently, the lab contains 124 persons among whom 60 PhD candidates, and runs
3932 ongoing French/European funded projects.
40Since its creation in 1984, TIMA funded 7 start ups, patented 36 inventions
41and had 243 PhD thesis defended.
42
43The System Level Synthesis Group (25 people including PhDs) is
44involved in several FP6, FP7, CATRENE and ANR projects.
45Its field of expertise is in CAD and architecture for Multiprocessor
46SoC and Hardware/Software interface.
47
48%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
49\subsubsection{\ubs}
50
51The Lab-STICC (Laboratoire des Sciences et Techniques de l'Information,
52de la Communication, et de la Connaissance), is a French CNRS laboratory
53(UMR 3192) that gathers 4 research centers in the west and south
54Brittany; from the Universitᅵ de Bretagne-Sud (UBS), the Universitᅵ de
55Bretagne Occidentale (UBO), and Telecom Bretagne (ENSTB).
56\\
57The Lab-STICC is composed of three departments: Microwave and equipments (MOM),
58Digital communications, Architectures and circuits (CACS) and Knowledge,
59information and decision (CID). The Lab-STICC represents a staff of 279
60people, including 115 researchers and 113 PhD students.
61The scientific production during the last 4 years represents 20
62books, 200 journal publications, 500 conference publications, 22
63patents, 69 PhDs diploma.
64\par
65The UBS/Lab-STICC laboratory is involved in several national research
66projects (e.g. RNTL : SystemC'Mantic, EPICURE - RNRT : MILPAT, ALIPTA,
67A3S - ANR : MoPCoM, SoCLib, Famous, RaaR, AFANA, Open-PEOPLE, ICTER ...),
68CMCU project (COSIP) and regional projects (e.g. ITR projects PALMYRE
69...). It is also involved in European Project (e.g. ITEA/SPICES,
70IST/AETHER ...). These projects are conducted through tight cooperation
71with national and international companies and organizations (e.g. France
72Telecom CNET, MATRA, CEA, ASTRIUM, THALES Com., THALES Avionics, AIRBUS,
73BarCo, STMicroelectronics, Alcatel-Lucent ...). Results of those or former
74projects are for example the high-level synthesis tool GAUT, the UHLS
75syntax and semantics-oriented editor, the DSP power estimation tool
76Soft-explorer or the co-design framework Design Trotter.
77\\
78\par
79The CACS department of the Lab-STICC (also referred as UBS/Lab-STICC),
80located in Lorient, is involved in COACH.
81The UBS/Lab-STICC is working on the design of complex electronic systems
82and circuits, especially but not exclusively focussing on real-time
83embedded systems, power and energy consumption optimization, high-level
84synthesis and IP design, digital communications, hardware/software
85co-design and ESL methodologies. The application targeted by the
86UBS/Lab-STICC are mainly from telecommunication and multimedia domains
87which enclose signal, image, video, vision, and communication processing.
88
89
90%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
91\subsubsection{\upmc}
92
93University Pierre et Marie Curie (UPMC)  is the largest university in France (7400 employees,38000 students).
94The Laboratoire d'Informatique de Paris 6 (LIP6) is the computer science laboratory of UPMC, hosting
95more than 400 researchers, under the umbrella of the CNRS (Centre National de la Recherche Scientifique).
96The \og System on Chip \fg Department of LIP6 consists of  80 people, including 40 PHD students.
97The research focus on CAD tools and methods for VLSI and System on Chip design.
98\parlf
99The annual budget is about 3 M{\texteuro}, and 1.5 M{\texteuro} are from research contracts.
100The SoC department has been involved in several european projects :IDPS, EVEREST, OMI-HIC, OMI-MACRAME,
101OMI-ARCHES, EUROPRO, COSY, Medea SMT, Medea MESA, Medea+ BDREAMS, Medea+ TSAR.
102\parlf
103The public domain VLSI CAD system ALLIANCE, developped at UPMC is installed in more than 200 universities worldwide.
104The LIP6 is in charge of the technical coordination of the SoCLib national project, and is hosting
105the SoCLib WEB server.
106In the SoCLin platform, the DSX tool is used for design space exploration.
107It helps the system designer to describe the coarse grain parallelism of the software application
108as a Task and Communication Graph, to configure the hardware architecture, and to map the
109multi-task software application on the multi-processors architecture.
110The DSX toll will be extended to support the FPGA target.
111Moreover, the LIP6 developped during the last 10 years the UGH tool for high level synthesis
112of control-dominated coprocessors.
113This tool will be modified to be integrated in the Coach design flow.
114\parlf
115Even if the preferred dissemination policy for the Coach design flow will be the free software policy,
116(following the SoCLib model), the SoC department is ready to support start-ups : Six startup companies
117(including FLEXRAS) have been created by former researchers from  the SoC department of LIP6 between 1997 and 2002.
118
119%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
120\subsubsection{\xilinx}
121
122\xilinx is the world leader in the domain of programmable logic circuits (FPGA).
123\xilinx develops in one hand several FPGA architectures (CoolRunner, Spartan and Virtex
124families) and in the other hand a software solution allowing exploiting the
125characteristics of these FPGA.
126\parlf
127The tools proposed can allow the designer to describe his architecture from modeling
128language (VHDL/Verilog) to an optimized architecture implemented to the selected
129technology.
130The team located at Grenoble is responsible of the logic synthesis tool development (XST)
131of the software solution, which aggregates all the steps allowing proceeding from a  HDL
132model to a technological netlist:
133\begin{itemize}
134  \item Compilation of HDL code and model generation at Register Transfer Level (RTL).
135  \item RTL model optimizations.
136  \item Inference and generation of optimized macro blocks (Finite states machine, counter).
137  \item Boolean equations generation for randomly logic.
138  \item Logical, mapping and timing optimizations.
139\end{itemize}
140\parlf
141The architectures developed by \xilinx offer a collection of technological primitives
142(variable complexity) from simple Boolean generators (LUT) to complex DSP blocks or memory
143and whether configurable processor cores (Pico and MicroBlaze families).
144This kind of architecture allows, thus, the designer to validate different
145hardware/software possibilities in a High Level Synthesis (HLS) framework.
146\parlf
147The classical optimization techniques focus, mainly, on the frequency aspects and on
148available resources use.
149The optimizations, taking into account the consumption criteria, become critical due to
150the fact of the increase of the architecture complexity and due to the use of FPGA
151component for low power applications.
152
153%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
154\subsubsection{\bull}
155
156\bull designs and develops servers and software for an open environment, integrating the
157most advanced technologies. It brings to its customers its expertise and know-how to help
158them in the transformation of their information systems and to optimize their IT
159infrastructure and their applications.
160\parlf
161\bull is particularly present in the public sector, banking, finance, telecommunication
162and industry sectors. Capitalizing on its wide experience, the Group has a thorough
163understanding of the business and specific processes of these sectors, thus enabling it to
164efficiently advise and to accompany its customers. Its distribution network spreads to
165over 100 countries worldwide.
166\parlf
167The team participating to the COACH project is from the Server Development Department
168based in Les Clayes-sous-Bois, France. The SD Department is in charge of developing
169hardware for open servers (e.g. NovaScale) and HPC solutions. Its main activities range
170from architecture specification, ASIC design/verification/prototyping to board design and
171include also specific EDA development to complement standard tools.
172
173%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
174\subsubsection{\thales}
175
176%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
177\subsubsection{\zied}
178
179%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
180\subsubsection{\navtel}
181
182\navtel was created in 1994 to develop flexible systems based on FPGAs and currently
183focuses on intelligent signal mining for knowlege based signal processing systems.
184The company main activity covers the following domains: satellite communication,
185aeronautics, imaging and security.
186\navtel dedicates about 70\% of its activity to client projects in satellite, aeronautical
187and imaging systems and 30\% to its own research programmes in collaboration with French
188and international partners.
189\parlf
190The multi disciplinary technical team comprises 6 engineers for signal processing and
191hardware development and one technician.
192\parlf
193\navtel has its own Ph.D program which includes in the past (classification technology
194and MIMO for FPGA implementation) and currently the preparation of a project for remote
195sensing with signal intelligence for satellite application. The company participates in
196national and European level projects contributing to a strategic alliance between academic
197and  industrial partners.\\
198The current research covers particle filter applications for communication and RADAR,
199Cognitive Radio, Satellite communication, embedded super computing and focuses on low
200power algorithms for implementation in FPGA and  soft computing.
201\parlf
202For manufacturing and industrialization, \navtel works with ISO certified partners.
203The company clients include the CNES, ThalÚs Alenia Space, ThalÚs Communication, EADS,
204Eutelsat, AIRBUS, Schlumberger. \navtel participates from the R\&D phase through to the
205system delivery.
206
207\begin{description}
208\item[Recognitions:]\mbox{}
209\begin{itemize}
210  \item EC Challenge+  programme for innovative projects (promotion 9)
211  \item Innovation and technology development \og Troph\'{e}es R\'{e}gion Centre \fg
212  \item Recognition by the French Senate for company creation  during the
213        \og Semaine de l'entrepreneur \fg 2005.
214\end{itemize}
215\end{description}
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