Changeset 99 for anr/section-6.1.tex

Timestamp:

Feb 8, 2010, 12:11:05 AM (14 years ago)

Author:

coach

Message:

IA: 1) mise en page et verification de 2, 2.1, 2.2 4.1. 2) entrer bull/xilinx/navtel dans 6.1 3) xilinx dans 7.

File:

• anr/section-6.1.tex (modified) (4 diffs)

anr/section-6.1.tex

@@ -90 +90 @@
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 \subsubsection{\upmc}
+
 University Pierre et Marie Curie (UPMC)  is the largest university in France (7400 employees,38000 students). 
 The Laboratoire d'Informatique de Paris 6 (LIP6) is the computer science laboratory of UPMC, hosting
 more than 400 researchers, under the umbrella of the CNRS (Centre National de la Recherche Scientifique). 
-The ￜ System on Chip ￜ Department of LIP6 consists of  80 people, including 40 PHD students. 
+The \og System on Chip \fg Department of LIP6 consists of  80 people, including 40 PHD students. 
 The research focus on CAD tools and methods for VLSI and System on Chip design. 
-\\
+\parlf
 The annual budget is about 3 M{\texteuro}, and 1.5 M{\texteuro} are from research contracts. 
 The SoC department has been involved in several european projects :IDPS, EVEREST, OMI-HIC, OMI-MACRAME, 
 OMI-ARCHES, EUROPRO, COSY, Medea SMT, Medea MESA, Medea+ BDREAMS, Medea+ TSAR. 
+\parlf
 The public domain VLSI CAD system ALLIANCE, developped at UPMC is installed in more than 200 universities worldwide.
 The LIP6 is in charge of the technical coordination of the SoCLib national project, and is hosting
@@ -110 +112 @@
 of control-dominated coprocessors.
 This tool will be modified to be integrated in the Coach design flow.
+\parlf
 Even if the preferred dissemination policy for the Coach design flow will be the free software policy,
 (following the SoCLib model), the SoC department is ready to support start-ups : Six startup companies 
@@ -115 +118 @@
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsubsection{\altera}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 \subsubsection{\xilinx}
 
+\xilinx is the world leader in the domain of programmable logic circuits (FPGA).
+\xilinx develops in one hand several FPGA architectures (CoolRunner, Spartan and Virtex
+families) and in the other hand a software solution allowing exploiting the
+characteristics of these FPGA.
+\parlf
+The tools proposed can allow the designer to describe his architecture from modeling
+language (VHDL/Verilog) to an optimized architecture implemented to the selected
+technology.
+The team located at Grenoble is responsible of the logic synthesis tool development (XST)
+of the software solution, which aggregates all the steps allowing proceeding from a  HDL
+model to a technological netlist:
+\begin{itemize}
+  \item Compilation of HDL code and model generation at Register Transfer Level (RTL).
+  \item RTL model optimizations.
+  \item Inference and generation of optimized macro blocks (Finite states machine, counter).
+  \item Boolean equations generation for randomly logic.
+  \item Logical, mapping and timing optimizations.
+\end{itemize}
+\parlf
+The architectures developed by \xilinx offer a collection of technological primitives
+(variable complexity) from simple Boolean generators (LUT) to complex DSP blocks or memory
+and whether configurable processor cores (Pico and MicroBlaze families).
+This kind of architecture allows, thus, the designer to validate different
+hardware/software possibilities in a High Level Synthesis (HLS) framework.
+\parlf
+The classical optimization techniques focus, mainly, on the frequency aspects and on
+available resources use.
+The optimizations, taking into account the consumption criteria, become critical due to
+the fact of the increase of the architecture complexity and due to the use of FPGA
+component for low power applications.
+
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 \subsubsection{\bull}
 
+\bull designs and develops servers and software for an open environment, integrating the
+most advanced technologies. It brings to its customers its expertise and know-how to help
+them in the transformation of their information systems and to optimize their IT
+infrastructure and their applications.
+\parlf
+\bull is particularly present in the public sector, banking, finance, telecommunication
+and industry sectors. Capitalizing on its wide experience, the Group has a thorough
+understanding of the business and specific processes of these sectors, thus enabling it to
+efficiently advise and to accompany its customers. Its distribution network spreads to
+over 100 countries worldwide.
+\parlf
+The team participating to the COACH project is from the Server Development Department
+based in Les Clayes-sous-Bois, France. The SD Department is in charge of developing
+hardware for open servers (e.g. NovaScale) and HPC solutions. Its main activities range
+from architecture specification, ASIC design/verification/prototyping to board design and
+include also specific EDA development to complement standard tools.
+
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 \subsubsection{\thales}
@@ -132 +180 @@
 \subsubsection{\navtel}
 
+\navtel was created in 1994 to develop flexible systems based on FPGAs and currently
+focuses on intelligent signal mining for knowlege based signal processing systems. 
+The company main activity covers the following domains: satellite communication,
+aeronautics, imaging and security.
+\navtel dedicates about 70\% of its activity to client projects in satellite, aeronautical
+and imaging systems and 30\% to its own research programmes in collaboration with French
+and international partners.
+\parlf
+The multi disciplinary technical team comprises 6 engineers for signal processing and
+hardware development and one technician.
+\parlf
+\navtel has its own Ph.D program which includes in the past (classification technology
+and MIMO for FPGA implementation) and currently the preparation of a project for remote
+sensing with signal intelligence for satellite application. The company participates in
+national and European level projects contributing to a strategic alliance between academic
+and  industrial partners.\\
+The current research covers particle filter applications for communication and RADAR,
+Cognitive Radio, Satellite communication, embedded super computing and focuses on low
+power algorithms for implementation in FPGA and  soft computing.
+\parlf
+For manufacturing and industrialization, \navtel works with ISO certified partners.
+The company clients include the CNES, ThalÚs Alenia Space, ThalÚs Communication, EADS,
+Eutelsat, AIRBUS, Schlumberger. \navtel participates from the R\&D phase through to the
+system delivery.
+
+\begin{description}
+\item[Recognitions:]\mbox{}
+\begin{itemize}
+  \item EC Challenge+  programme for innovative projects (promotion 9)
+  \item Innovation and technology development \og Troph\'{e}es R\'{e}gion Centre \fg
+  \item Recognition by the French Senate for company creation  during the
+        \og Semaine de l'entrepreneur \fg 2005.
+\end{itemize}
+\end{description}