source: anr/section-6.1.tex @ 131

Last change on this file since 131 was 123, checked in by coach, 15 years ago

IA: 1) enter thales + zied 2) m.a.p

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2\subsubsection{\inria (CAIRN \& COMPSYS teams)}
3
4Inria, the French national institute for research in computer science
5and control, operating under the dual authority of the Ministry of
6Research and the Ministry of Industry, is dedicated to fundamental and
7applied research in information and communication science and
8technology (ICST). The Institute also plays a major role in technology
9transfer by fostering training through research, diffusion of
10scientific and technical information, development, as well as
11providing expert advice and participating in international programs.
12
13By playing a leading role in the scientific community in the field and
14being in close contact with industry, INRIA is a major participant in
15the development of ICST in France. Throughout its eight research
16centres in Rocquencourt, Rennes, Sophia Antipolis, Grenoble, Nancy,
17Bordeaux, Lille and Saclay, INRIA has a workforce of 3 800, 2 800 of
18whom are scientists from INRIA and INRIA's partner organizations such
19as CNRS (the French National Center for Scientific Research),
20universities and leading engineering schools. They work in 168 joint
21research project-teams. Many INRIA researchers are also professors and
22approximately 1 000 doctoral students work on theses as part of INRIA
23research project-teams.
24
25INRIA develops many partnerships with industry and fosters technology
26transfer and company foundation in the field of ICST - some ninety
27companies have been founded with the support of INRIA-Transfert, a
28subsidiary of INRIA, specialized in guiding, evaluating, qualifying,
29and financing innovative high-tech IT start-up companies. INRIA is
30involved in standardization committees such as the IETF, ISO and the
31W3C of which INRIA was the European host from 1995 to 2002.
32
33INRIA maintains important international relations and exchanges. In
34Europe, INRIA is a member of ERCIM which brings together research
35institutes from 19 European countries. INRIA is a partner in about 120
36FP6 actions and 40 FP7 actions, mainly in the ICST field. INRIA also
37collaborates with numerous scientific and academic institutions abroad
38(joint laboratories such as LIAMA, associated research teams, training
39and internship programs).\\
40
41Two \inria project-teams participate to this project.
42\begin{itemize}
43\item CAIRN. The CAIRN group of INRIA Rennes -- Bretagne Atlantique study
44reconfigurable system-on-chip, i.e. hardware systems whose
45configuration may change before or even during execution. To this end,
46CAIRN has 13 permanent researchers and a variable number of PhD students, post-docs and engineers.
47CAIRN intends to approach reconfigurable architectures from three
48angles: the invention of new reconfigurable platforms, the development
49of associated transformation, compilation and synthesis tools, and the
50exploration of the interaction between algorithms and architectures.
51CAIRN is a joint team with CNRS, INSA of Rennes, University of Rennes 1 and ENS Cachan.
52
53\item COMPSYS. The Compsys group of Ecole Normale Sup\'erieure de Lyon is a project-team
54of INRIA Rh\^one-Alpes and a part of Laboratoire de l'Informatique du
55Parall\'elisme (LIP), UMR 5668 of CNRS. It has four permanent researchers
56and a variable number of PhD students and post-docs. Its field of
57expertise is compilation for embedded system, optimizing compilers
58and automatic parallelization. It  has authored or contributed to
59several well known libraries for linear programming, polyhedra manipulation
60and optimization in general. It has strong industrial cooperations, notably
61with ST Microelectronics and Thales.
62\end{itemize}
63
64
65%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
66\subsubsection{\tima}
67The TIMA laboratory ("Techniques of Informatics and Microelectronics
68for integrated systems Architecture") is a public research laboratory
69sponsored by Centre National de la Recherche Scientifique (CNRS, UMR5159),
70Grenoble Institute of Technology (Grenoble-INP) and Universitᅵ Joseph Fourier
71(UJF).
72The research topics cover the specification, design, verification, test,
73CAD tools and design methods for integrated systems, from analog and
74digital components on one end of the spectrum, to multiprocessor
75Systems-on-Chip together with their basic operating system on the other end.
76
77Currently, the lab employs 124 persons among which 60 PhD candidates, and runs
7832 ongoing French/European funded projects.
79Since its creation in 1984, TIMA funded 7 startups, patented 36 inventions
80and had 243 PhD thesis defended.
81
82The System Level Synthesis Group (25 people including PhDs) is
83involved in several FP6, FP7, CATRENE and ANR projects.
84Its field of expertise is in CAD and architecture for Multiprocessor
85SoC and Hardware/Software interface.
86
87%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
88\subsubsection{\ubs}
89
90The Lab-STICC (Laboratoire des Sciences et Techniques de l'Information,
91de la Communication, et de la Connaissance), is a French CNRS laboratory
92(UMR 3192) that groups 4 research centers in the west and south
93Brittany: the Universit\'e de Bretagne-Sud (UBS), the Universit\'e de
94Bretagne Occidentale (UBO), and Telecom Bretagne (ENSTB).
95\\
96The Lab-STICC is composed of three departments: Microwave and equipments (MOM),
97Digital communications, Architectures and circuits (CACS) and Knowledge,
98information and decision (CID). The Lab-STICC represents a staff of 279
99peoples, including 115 researchers and 113 PhD students.
100The scientific production during the last 4 years represents 20
101books, 200 journal publications, 500 conference publications, 22
102patents, 69 PhDs diploma.
103\par
104The UBS/Lab-STICC laboratory is involved in several national research
105projects (e.g. RNTL : SystemC'Mantic, EPICURE - RNRT : MILPAT, ALIPTA,
106A3S - ANR : MoPCoM, SoCLib, Famous, RaaR, AFANA, Open-PEOPLE, ICTER ...),
107CMCU project (COSIP) and regional projects (e.g. ITR projects PALMYRE
108...). It is also involved in European Project (e.g. ITEA/SPICES,
109IST/AETHER ...). These projects are conducted through tight cooperation
110with national and international companies and organizations (e.g. France
111Telecom CNET, MATRA, CEA, ASTRIUM, \thales Com., \thales Avionics, AIRBUS,
112BarCo, STMicroelectronics, Alcatel-Lucent ...). Results of those or former
113projects are for example the high-level synthesis tool GAUT, the UHLS
114syntax and semantics-oriented editor, the DSP power estimation tool
115Soft-explorer or the co-design framework Design Trotter.
116\\
117\par
118The CACS department of the Lab-STICC (also referred as UBS/Lab-STICC),
119located in Lorient, is involved in COACH.
120The UBS/Lab-STICC is working on the design of complex electronic systems
121and circuits, especially but not exclusively focussing on real-time
122embedded systems, power and energy consumption optimization, high-level
123synthesis and IP design, digital communications, hardware/software
124co-design and ESL methodologies. The application targeted by the
125UBS/Lab-STICC are mainly from telecommunication and multimedia domains
126which enclose signal, image, video, vision, and communication processing.
127
128
129%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
130\subsubsection{\upmc}
131
132University Pierre et Marie Curie (UPMC)  is the largest university in France (7400 employees,38000 students).
133The Laboratoire d'Informatique de Paris 6 (LIP6) is the computer science laboratory of UPMC, hosting
134more than 400 researchers, under the umbrella of the CNRS (Centre National de la Recherche Scientifique).
135The \og System on Chip \fg Department of LIP6 consists of  80 people, including 40 PHD students.
136The research focus on CAD tools and methods for VLSI and System on Chip design.
137\parlf
138The annual budget is about 3 M{\texteuro}, and 1.5 M{\texteuro} are from research contracts.
139The SoC department has been involved in several european projects :IDPS, EVEREST, OMI-HIC, OMI-MACRAME,
140OMI-ARCHES, EUROPRO, COSY, Medea SMT, Medea MESA, Medea+ BDREAMS, Medea+ TSAR.
141\parlf
142The public domain VLSI CAD system ALLIANCE, developped at UPMC is installed in more than 200 universities worldwide.
143The LIP6 is in charge of the technical coordination of the SoCLib national project, and is hosting
144the SoCLib WEB server.
145In the SoCLin platform, the DSX tool is used for design space exploration.
146It helps the system designer to describe the coarse grain parallelism of the software application
147as a Task and Communication Graph, to configure the hardware architecture, and to map the
148multi-task software application on the multi-processors architecture.
149The DSX toll will be extended to support the FPGA target.
150Moreover, the LIP6 developped during the last 10 years the UGH tool for high level synthesis
151of control-dominated coprocessors.
152This tool will be modified to be integrated in the Coach design flow.
153\parlf
154Even if the preferred dissemination policy for the Coach design flow will be the free software policy,
155(following the SoCLib model), the SoC department is ready to support start-ups : Six startup companies
156(including \zied) have been created by former researchers from  the SoC department of LIP6 between 1997 and 2002.
157
158%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
159\subsubsection{\xilinx}
160
161\xilinx is the world leader in the domain of programmable logic circuits (FPGA).
162\xilinx develops on one hand several FPGA architectures (CoolRunner, Spartan and Virtex
163families) and in the other hand a software solution allowing exploiting the
164characteristics of these FPGA.
165\parlf
166The tools proposed allow the designer to describe his architecture from a modeling
167language (VHDL/Verilog) to an optimized architecture implemented to the selected
168technology.
169The team located at Grenoble is responsible of the logic synthesis tool development (XST)
170of the software solution, which aggregates all the steps allowing proceeding from a  HDL
171model to a technological netlist:
172\begin{itemize}
173  \item Compilation of HDL code and model generation at Register Transfer Level (RTL).
174  \item RTL model optimizations.
175  \item Inference and generation of optimized macro blocks (Finite states machine, counter).
176  \item Boolean equations generation for random logic.
177  \item Logical, mapping and timing optimizations.
178\end{itemize}
179\parlf
180The architectures developed by \xilinx offer a collection of technological primitives
181(variable complexity) from simple Boolean generators (LUT) to complex DSP blocks or memory
182and even configurable processor cores (Pico and MicroBlaze families).
183This kind of architecture allows, therefore, the designer to validate different
184hardware/software possibilities in a High Level Synthesis (HLS) framework.
185\parlf
186The classical optimization techniques focus, mainly, on the frequency aspects and on
187available resources use.
188The optimizations, taking into account the consumption criteria, become critical due to
189the fact of the increase of the architecture complexity and due to the use of FPGA
190component for low power applications.
191
192%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
193\subsubsection{\bull}
194
195\bull designs and develops servers and software for an open environment, integrating the
196most advanced technologies. It brings to its customers its expertise and know-how to help
197them in the transformation of their information systems and to optimize their IT
198infrastructure and their applications.
199\parlf
200\bull is particularly present in the public sector, banking, finance, telecommunication
201and industry sectors. Capitalizing on its wide experience, the Group has a thorough
202understanding of the business and specific processes of these sectors, thus enabling it to
203efficiently advise and to accompany its customers. Its distribution network spreads to
204over 100 countries worldwide.
205\parlf
206The team participating to the COACH project is from the Server Development Department
207based in Les Clayes-sous-Bois, France. The SD Department is in charge of developing
208hardware for open servers (e.g. NovaScale) and HPC solutions. Its main activities range
209from architecture specification, ASIC design/verification/prototyping to board design and
210include also specific EDA development to complement standard tools.
211
212%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
213\subsubsection{\thales}
214
215\thales is a world leader for mission critical information systems, with activities in 3
216core businesses: aerospace (with all major aircraft manufacturers as customers), defence,
217and security (including ground transportation solutions). It employs 68000 people
218worldwide, and is present in 50 countries.  \thales develops its strategic capabilities in
219component, software and system engineering and architectures through its R \& T organization.
220Its six Divisions manage their strategy and technical co-ordination per domain with
221hundreds of Units in these Divisions developing their technical activities in close
222relationship with their market. In this environment, \thales Research \& Technology
223operates at the corporate level as the technical community network architect, in charge of
224developing upstream and \thales-wide R \& T activities, with vision and visibility.
225In support of \thales applications, TRT's mission is also to anticipate and speed up
226technology transfer from research to development in Divisions by developing collaborations
227in R\&T.
228
229Thales is international, but Europe-centered. Research \& Development activities are
230disseminated, and corporate Research and Technology is concentrated in Centres in France,
231the United Kingdom and the Netherlands.
232The R\&T in Thales emphasizes more particularly on critical information systems,
233processing, control and cognitive systems, and autonomous systems.
234
235A key mission of our R\&T centres is to have a bi-directional transfer, or “impedance
236matching” function between the scientific research network and the corresponding
237businesses. Benefiting from its presence and visibility on the international scene in
238advanced sciences, technology and software, \thales Research \& Technology is perceived as
239a valuable partner of the best research centres (academic or industrial) through
240recognized scientists and research engineer participation in collaborative projects.
241The TRT’s Information Science and Technology Group is able to develop innovative solutions
242along the information chain exploiting sensors data, through expertise in: computational
243architectures in embedded systems, typically suitable for autonomous system environments,
244mathematics and technologies for decision involving information fusion and cognitive
245processing, and cooperative technologies including man system interaction.
246The Embedded System Laboratory (ESL) of TRT involved in the COACH project is part of the
247Information Science and Technology Group.
248
249Like other labs of TRT, ESL is in charge of making the link between the needs from Thales
250business units and the emerging technologies, in particular through assessment and
251de-risking studies.
252It has a long experience on parallel architectures design, in particular on SIMD
253architectures used for image processing and signal processing applications and on
254reconfigurable architectures.
255ESL is also strongly involved in studies on programming tools for these types of
256architectures and has developed the SpearDE tool used in this project.
257The laboratory had coordinated the FP6 IST MORPHEUS project on reconfigurable technology,
258being highly involved in the associated programming toolset.
259
260The team is also involved in
261the FP6 IST FET AETHER project on self-adaptability technologies and coordinates national
262projects on MPSoC architecture and tools like the \verb+Ter@ops+ project (P\^{o}le de
263Comp\'{e}titivit\'{e} \verb+System@tic+) dedicated to the design of a MPSoC for intensive
264computing embedded systems.
265
266%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
267\subsubsection{\zied}
268
269\zied is an innovative start-up specialized in the conception of configurable circuits
270and the development of CAD tools. \zied provides a complete front-to-back-end generator
271of "hardware" reprogrammable IP cores that can be embedded in ASIC and ASSP SoC designs.
272\zied solution is based on a patented FPGA architecture delivering an unprecedented
273level of logic density. This high capacity is accessible using a traditional RTL flow from
274Verilog/VHDL synthesis all the way to bitstream generation.
275
276\zied is a spin-off from LIP6 (Laboratoire Informatique Paris 6) and was awarded at the
277French National Competition for Business Startup and Innovative Technology in 2007 and
2782009 in “emergence” and “creation” categories respectively.
279
280%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
281\subsubsection{\navtel}
282
283\navtel was created in 1994 to develop flexible systems based on FPGAs and currently
284focuses on intelligent signal mining for knowlege based signal processing systems.
285The company main activity covers the following domains: satellite communication,
286aeronautics, imaging and security.
287\navtel dedicates about 70\% of its activity to client projects in satellite, aeronautical
288and imaging systems and 30\% to its own research programmes in collaboration with French
289and international partners.
290\parlf
291The multi disciplinary technical team comprises 6 engineers for signal processing and
292hardware development and one technician.
293\parlf
294\navtel has its own Ph.D program which includes in the past (classification technology
295and MIMO for FPGA implementation) and currently the preparation of a project for remote
296sensing with signal intelligence for satellite application. The company participates in
297national and European level projects contributing to a strategic alliance between academic
298and  industrial partners.\\
299The current research covers particle filter applications for communication and RADAR,
300Cognitive Radio, Satellite communication, embedded super computing and focuses on low
301power algorithms for implementation in FPGA and  soft computing.
302\parlf
303For manufacturing and industrialization, \navtel works with ISO certified partners.
304The company clients include the CNES, ThalÚs Alenia Space, ThalÚs Communication, EADS,
305Eutelsat, AIRBUS, Schlumberger. \navtel participates from the R\&D phase through to the
306system delivery.
307
308\begin{description}
309\item[Recognitions:]\mbox{}
310\begin{itemize}
311  \item EC Challenge+  programme for innovative projects (promotion 9)
312  \item Innovation and technology development \og Troph\'{e}es R\'{e}gion Centre \fg
313  \item Recognition by the French Senate for company creation  during the
314        \og Semaine de l'entrepreneur \fg 2005.
315\end{itemize}
316\end{description}
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