source: anr/section-6.1.tex @ 99

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\subsubsection{\irisa}

The CAIRN group is an INRIA - Bretagne Atlantique project and a part of IRISA, UMR
6074. CAIRN members are affiliated from University of Rennes\~1 or Ecole Normale 
Supérieure de Cachan. the goal of CAIRN is to study reconfigurable system-on-chip, 
i.e. hardware systems whose configuration may change before or even during execution. 
To this end, CAIRN intends to approach reconfigurable architectures from three angles: 
the invention of new reconfigurable platforms, the development of associated 
transformation, compilation and synthesis tools, and the exploration of the interaction 
between algorithms and architectures.

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\subsubsection{\lip}
The Compsys group of Ecole Normale Sup\'erieure de Lyon is a project-team
of INRIA Rh\^one-Alpes and a part of Laboratoire de l'Informatique du
Parall\'elisme (LIP), UMR 5668 of CNRS. It has four permanent researchers
and a variable number of PhD students and post-docs. Its field of
expertise is compilation for embedded system, optimizing compilers
and automatic parallelization. It  has authored or contributed to
several well known libraries for linear programming, polyhedra manipulation
and optimization in general. It has strong industrial cooperations, notably
with ST Microelectonics and Thales.


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\subsubsection{\tima}
The TIMA laboratory ("Techniques of Informatics and Microelectronics
for integrated systems Architecture") is a public research laboratory
sponsored by Centre National de la Recherche Scientifique (CNRS, UMR5159),
Grenoble Institute of Technology (Grenoble-INP) and Universitￜ Joseph Fourier
(UJF).
The research topics cover the specification, design, verification, test,
CAD tools and design methods for integrated systems, from analog and
digital components on one end of the spectrum, to multiprocessor
Systems-on-Chip together with their basic operating system on the other end.

Currently, the lab contains 124 persons among whom 60 PhD candidates, and runs
32 ongoing French/European funded projects.
Since its creation in 1984, TIMA funded 7 start ups, patented 36 inventions
and had 243 PhD thesis defended.

The System Level Synthesis Group (25 people including PhDs) is
involved in several FP6, FP7, CATRENE and ANR projects.
Its field of expertise is in CAD and architecture for Multiprocessor
SoC and Hardware/Software interface.

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\subsubsection{\ubs}

The Lab-STICC (Laboratoire des Sciences et Techniques de l'Information, 
de la Communication, et de la Connaissance), is a French CNRS laboratory 
(UMR 3192) that gathers 4 research centers in the west and south 
Brittany; from the Universitￜ de Bretagne-Sud (UBS), the Universitￜ de 
Bretagne Occidentale (UBO), and Telecom Bretagne (ENSTB). 
\\
The Lab-STICC is composed of three departments: Microwave and equipments (MOM), 
Digital communications, Architectures and circuits (CACS) and Knowledge, 
information and decision (CID). The Lab-STICC represents a staff of 279 
people, including 115 researchers and 113 PhD students. 
The scientific production during the last 4 years represents 20 
books, 200 journal publications, 500 conference publications, 22 
patents, 69 PhDs diploma. 
\par
The UBS/Lab-STICC laboratory is involved in several national research 
projects (e.g. RNTL : SystemC'Mantic, EPICURE - RNRT : MILPAT, ALIPTA, 
A3S - ANR : MoPCoM, SoCLib, Famous, RaaR, AFANA, Open-PEOPLE, ICTER ...), 
CMCU project (COSIP) and regional projects (e.g. ITR projects PALMYRE 
...). It is also involved in European Project (e.g. ITEA/SPICES, 
IST/AETHER ...). These projects are conducted through tight cooperation 
with national and international companies and organizations (e.g. France 
Telecom CNET, MATRA, CEA, ASTRIUM, THALES Com., THALES Avionics, AIRBUS, 
BarCo, STMicroelectronics, Alcatel-Lucent ...). Results of those or former 
projects are for example the high-level synthesis tool GAUT, the UHLS 
syntax and semantics-oriented editor, the DSP power estimation tool 
Soft-explorer or the co-design framework Design Trotter.
\\
\par
The CACS department of the Lab-STICC (also referred as UBS/Lab-STICC), 
located in Lorient, is involved in COACH. 
The UBS/Lab-STICC is working on the design of complex electronic systems 
and circuits, especially but not exclusively focussing on real-time 
embedded systems, power and energy consumption optimization, high-level 
synthesis and IP design, digital communications, hardware/software 
co-design and ESL methodologies. The application targeted by the 
UBS/Lab-STICC are mainly from telecommunication and multimedia domains 
which enclose signal, image, video, vision, and communication processing.


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\subsubsection{\upmc}

University Pierre et Marie Curie (UPMC)  is the largest university in France (7400 employees,38000 students). 
The Laboratoire d'Informatique de Paris 6 (LIP6) is the computer science laboratory of UPMC, hosting
more than 400 researchers, under the umbrella of the CNRS (Centre National de la Recherche Scientifique). 
The \og System on Chip \fg Department of LIP6 consists of  80 people, including 40 PHD students. 
The research focus on CAD tools and methods for VLSI and System on Chip design. 
\parlf
The annual budget is about 3 M{\texteuro}, and 1.5 M{\texteuro} are from research contracts. 
The SoC department has been involved in several european projects :IDPS, EVEREST, OMI-HIC, OMI-MACRAME, 
OMI-ARCHES, EUROPRO, COSY, Medea SMT, Medea MESA, Medea+ BDREAMS, Medea+ TSAR. 
\parlf
The public domain VLSI CAD system ALLIANCE, developped at UPMC is installed in more than 200 universities worldwide.
The LIP6 is in charge of the technical coordination of the SoCLib national project, and is hosting
the SoCLib WEB server.
In the SoCLin platform, the DSX tool is used for design space exploration.
It helps the system designer to describe the coarse grain parallelism of the software application
as a Task and Communication Graph, to configure the hardware architecture, and to map the 
multi-task software application on the multi-processors architecture.
The DSX toll will be extended to support the FPGA target.
Moreover, the LIP6 developped during the last 10 years the UGH tool for high level synthesis
of control-dominated coprocessors.
This tool will be modified to be integrated in the Coach design flow.
\parlf
Even if the preferred dissemination policy for the Coach design flow will be the free software policy,
(following the SoCLib model), the SoC department is ready to support start-ups : Six startup companies 
(including FLEXRAS) have been created by former researchers from  the SoC department of LIP6 between 1997 and 2002.

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\subsubsection{\xilinx}

\xilinx is the world leader in the domain of programmable logic circuits (FPGA).
\xilinx develops in one hand several FPGA architectures (CoolRunner, Spartan and Virtex
families) and in the other hand a software solution allowing exploiting the
characteristics of these FPGA.
\parlf
The tools proposed can allow the designer to describe his architecture from modeling
language (VHDL/Verilog) to an optimized architecture implemented to the selected
technology.
The team located at Grenoble is responsible of the logic synthesis tool development (XST)
of the software solution, which aggregates all the steps allowing proceeding from a  HDL
model to a technological netlist:
\begin{itemize}
  \item Compilation of HDL code and model generation at Register Transfer Level (RTL).
  \item RTL model optimizations.
  \item Inference and generation of optimized macro blocks (Finite states machine, counter).
  \item Boolean equations generation for randomly logic.
  \item Logical, mapping and timing optimizations.
\end{itemize}
\parlf
The architectures developed by \xilinx offer a collection of technological primitives
(variable complexity) from simple Boolean generators (LUT) to complex DSP blocks or memory
and whether configurable processor cores (Pico and MicroBlaze families).
This kind of architecture allows, thus, the designer to validate different
hardware/software possibilities in a High Level Synthesis (HLS) framework.
\parlf
The classical optimization techniques focus, mainly, on the frequency aspects and on
available resources use.
The optimizations, taking into account the consumption criteria, become critical due to
the fact of the increase of the architecture complexity and due to the use of FPGA
component for low power applications.

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\subsubsection{\bull}

\bull designs and develops servers and software for an open environment, integrating the
most advanced technologies. It brings to its customers its expertise and know-how to help
them in the transformation of their information systems and to optimize their IT
infrastructure and their applications.
\parlf
\bull is particularly present in the public sector, banking, finance, telecommunication
and industry sectors. Capitalizing on its wide experience, the Group has a thorough
understanding of the business and specific processes of these sectors, thus enabling it to
efficiently advise and to accompany its customers. Its distribution network spreads to
over 100 countries worldwide.
\parlf
The team participating to the COACH project is from the Server Development Department
based in Les Clayes-sous-Bois, France. The SD Department is in charge of developing
hardware for open servers (e.g. NovaScale) and HPC solutions. Its main activities range
from architecture specification, ASIC design/verification/prototyping to board design and
include also specific EDA development to complement standard tools.

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\subsubsection{\thales}

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\subsubsection{\zied}

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\subsubsection{\navtel}

\navtel was created in 1994 to develop flexible systems based on FPGAs and currently
focuses on intelligent signal mining for knowlege based signal processing systems. 
The company main activity covers the following domains: satellite communication,
aeronautics, imaging and security.
\navtel dedicates about 70\% of its activity to client projects in satellite, aeronautical
and imaging systems and 30\% to its own research programmes in collaboration with French
and international partners.
\parlf
The multi disciplinary technical team comprises 6 engineers for signal processing and
hardware development and one technician.
\parlf
\navtel has its own Ph.D program which includes in the past (classification technology
and MIMO for FPGA implementation) and currently the preparation of a project for remote
sensing with signal intelligence for satellite application. The company participates in
national and European level projects contributing to a strategic alliance between academic
and  industrial partners.\\
The current research covers particle filter applications for communication and RADAR,
Cognitive Radio, Satellite communication, embedded super computing and focuses on low
power algorithms for implementation in FPGA and  soft computing.
\parlf
For manufacturing and industrialization, \navtel works with ISO certified partners.
The company clients include the CNES, ThalÚs Alenia Space, ThalÚs Communication, EADS,
Eutelsat, AIRBUS, Schlumberger. \navtel participates from the R\&D phase through to the
system delivery.

\begin{description}
\item[Recognitions:]\mbox{}
\begin{itemize}
  \item EC Challenge+  programme for innovative projects (promotion 9)
  \item Innovation and technology development \og Troph\'{e}es R\'{e}gion Centre \fg
  \item Recognition by the French Senate for company creation  during the
        \og Semaine de l'entrepreneur \fg 2005.
\end{itemize}
\end{description}