1 | \anrdoc{Décrire le contexte économique, social, réglementaire⊠dans lequel se |
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2 | situe le projet en présentant une analyse des enjeux sociaux, économiques, |
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3 | environnementaux, industriels⊠Donner si possible des arguments chiffrés, par |
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4 | exemple, pertinence et portée du projet par rapport à la demande économique |
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5 | (analyse du marché, analyse des tendances), analyse de la concurrence, |
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6 | indicateurs de réduction de coûts, perspectives de marchés (champs |
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7 | dâapplication, âŠ). Indicateurs des gains environnementaux, cycle de vie.} |
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8 | % |
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9 | \subsubsection*{Predominance of FPGA in the global electronic market} |
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10 | \begin{table}\leavevmode\center |
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11 | \begin{small}\begin{tabular}{|l|l|l|l|}\hline |
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12 | Segment & 2010 & 2011 & 2012 \\\hline\hline |
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13 | Communications & 1,867 & 1,946 & 2,096 \\ |
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14 | High end & 467 & 511 & 550 \\\hline |
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15 | Consumer & 550 & 592 & 672 \\ |
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16 | High end & 53 & 62 & 75 \\\hline |
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17 | Automotive & 243 & 286 & 358 \\ |
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18 | High end & - & - & - \\\hline |
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19 | Industrial & 1,102 & 1,228 & 1,406 \\ |
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20 | High end & 177 & 188 & 207 \\\hline |
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21 | Military/Aereo & 566 & 636 & 717 \\ |
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22 | High end & 56 & 65 & 82 \\\hline\hline |
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23 | Total FPGA/PLD & 4,659 & 5,015 & 5,583 \\ |
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24 | Total High-End FPGA & 753 & 826 & 914 \\\hline |
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25 | \end{tabular}\end{small} |
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26 | \caption{\label{fpga_market} Gartner estimation of worldwide FPGA/PLD consumption (Millions \$)} |
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27 | \end{table} |
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28 | % |
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29 | Microelectronic components allow the integration of complex functions into products, increases |
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30 | commercial attractivity of these products and improves their competitivity. |
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31 | Multimedia and tele-communication sectors have taken advantage from microelectronics facilities |
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32 | thanks to the developpment of design methodologies and tools for embedded systems. |
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33 | Unfortunately, the Non Recurring Engineering (NRE) costs involded in the design |
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34 | and manufacturing ASICs is very high. |
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35 | An IC foundry costs several billions of euros and the fabrication of a specific circuit |
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36 | costs several millions. For example a conservative estimate for a 65nm ASIC project is 10 |
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37 | million USD. |
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38 | Consequently, it is more and more unaffordable to design and fabricate ASICs for low and medium |
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39 | volume markets. |
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40 | % |
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41 | \subsubsection*{FPGAs and Embedded Systems} |
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42 | Today, FPGAs become important actors in the computational domain that was originally dominated |
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43 | by microprocessors and ASICs. Just like microprocessors, FPGA based systems can be reprogrammed |
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44 | on a per-application basis. For many applications, FPGAs offer significant performance benefits over |
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45 | microprocessors implementation. There is still a performance degradation of one order |
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46 | of magnitude versus an equivalent ASIC implementations, but low cost |
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47 | (500 euros to 10K euros), fast time-to-market and flexibility of FPGAs make them an attractive |
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48 | choice for low-to-medium volume applications. |
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49 | Since their introduction in the mid eighties, FPGAs evolved from a simple, |
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50 | low-capacity gate array to devices (\altera STRATIX III, \xilinx Virtex V) that |
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51 | provide a mix of coarse-grained data path units, memory blocks, microprocessor cores, |
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52 | on chip A/D conversion, and gate counts by millions. This high logic capacity allows to implement |
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53 | complex systems like multi-processors platform with application dedicated coprocessors. |
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54 | Table~\ref{fpga_market} shows the estimation of the FPGA worldwide market in the next years in |
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55 | various application domains. The ``high end'' lines concern only FPGA with high logic |
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56 | capacity for complex system implementations. |
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57 | This market is in significant expansion and is estimated to 914\,M\$ in 2012. |
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58 | %The HPC market size is estimated today by FPGA providers at 214\,M\$. |
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59 | %Using FPGA limits the NRE costs to the design cost. |
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60 | %This boosts the developpment of automatic design tools and methodologies. |
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61 | % |
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62 | \subsubsection*{FPGAs and High Performance Computing} |
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63 | Today, several companies (Atipa, blue-arc, Bull, Chelsio, Convey, CRAY, DataDirect, DELL, hp, |
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64 | Wild Systems, IBM, Intel, Microsoft, Myricom, NEC, nvidia etc) are making systems where demand |
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65 | for very high performance (HPC) primes over other requirements. They tend to use the highest |
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66 | performing devices like Multi-core CPUs, GPUs, large FPGAs, custom ICs and the most innovative |
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67 | architectures and algorithms. These companies show up in different "traditional" applications and market |
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68 | segments like computing clusters (ad-hoc), servers and storage, networking and Telecom, ASIC |
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69 | emulation and prototyping, military/aereo etc. The HPC market size is estimated today by FPGA providers |
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70 | at 214\,M\$. |
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71 | This market is dominated by Multi-core CPUs and GPUs based solutions and the expansion |
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72 | of FPGA-based solutions is limited by the lack of design automation. |
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73 | % |
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74 | \subsubsection*{Evolution of architectures} |
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75 | Nowadays processors mixing core and programmable matrix are available on the market (eg. Intel ATOM E600C). |
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76 | "Donald Newell, AMD technical manager, envisions that such circuits will be at the heart of most of the electronic |
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77 | products (eg. PDAs and nomad items) and even personal computers. |
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78 | To take benefit of such architecture, developping and deploying application will require innovative codesign methods and tools. |
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79 | |
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80 | % |
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81 | \subsubsection*{COACH's contribution to this evolution} |
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82 | Nowadays, there are no commercial or academic tools covering the whole design flow |
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83 | from the system level specification to the bitstream generation neither for embedded system design |
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84 | nor for HPC. |
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85 | \begin{center}\begin{minipage}{.9\linewidth}\textit{ |
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86 | The aim of the COACH project is to integrate all these design steps into a single design framework |
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87 | and to allow \textbf{pure software} developpers to design embedded systems. |
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88 | }\end{minipage}\end{center} |
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89 | % |
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90 | The COACH project proposes an open-source framework for mapping multi-tasks software applications |
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91 | on Field Programmable Gate Array circuits (FPGA). |
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92 | It aims to propose solutions to the societal/economical challenges by |
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93 | providing SMEs novel design capabilities enabling them to increase their |
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94 | design productivity with design exploration and synthesis methods that are placed on top |
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95 | of the state-of-the-art methods. |
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96 | We believe that the combination of a design environment dedicated to software developpers |
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97 | and FPGA targets, |
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98 | will allow small and even very small companies to propose embedded system and accelerating solutions |
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99 | for standard software applications with attractive and competitive prices. |
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100 | This new market may explode in the same way as the micro-computer market in the eighties, |
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101 | whose success was due to the low cost of the first micro-processors (compared to main frames) |
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102 | and the advent of high level programming languages which allowed a high number of programmers |
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103 | to launch start-ups in software engineering. |
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