Changeset 307 for anr/section-issues.tex

Timestamp:

Jan 13, 2011, 7:14:58 PM (14 years ago)

Author:

coach

Message:

Modifications EV: inputs MDS

File:

• anr/section-issues.tex (modified) (4 diffs)

anr/section-issues.tex

@@ -6 +6 @@
 indicateurs de réduction de coûts, perspectives de marchés (champs
 d’application, 
). Indicateurs des gains environnementaux, cycle de vie.}
-
-
+%
+\subsubsection*{Predominance of FPGA in the global electronic market}
 \begin{table}\leavevmode\center
 \begin{small}\begin{tabular}{|l|l|l|l|}\hline
@@ -38 +38 @@
 Consequently, it is more and more unaffordable to design and fabricate ASICs for low and medium
 volume markets.
-\parlf
+%
+\subsubsection*{FPGAs and Embedded Systems}
 Today, FPGAs become important actors in the computational domain that was originally dominated
 by microprocessors and ASICs. Just like microprocessors, FPGA based systems can be reprogrammed
@@ -59 +60 @@
 %This boosts the developpment of automatic design tools and methodologies.
 %
-\parlf
+\subsubsection*{FPGAs and High Performance Computing}
 Today, several companies (Atipa, blue-arc, Bull, Chelsio, Convey, CRAY, DataDirect, DELL, hp, 
 Wild Systems, IBM, Intel, Microsoft, Myricom, NEC, nvidia etc) are making systems where demand 
@@ -70 +71 @@
 This market is dominated by Multi-core CPUs and GPUs based solutions and the expansion
 of FPGA-based solutions is limited by the lack of design automation.
-\\
-\\
+%
+\subsubsection*{Evolution of architectures}
+Nowadays processors mixing core and programmable matrix are available on the market (eg. Intel ATOM E600C).
+"Donald Newell, AMD technical manager, envisions that such circuits will be at the heart of most of the electronic 
+products (eg. PDAs and nomad items) and even personal computers. 
+To take benefit of such architecture, developping and deploying application will require innovative codesign methods and tools.
+
+%
+\subsubsection*{COACH's contribution to this evolution}
 Nowadays, there are no commercial or academic tools covering the whole design flow
 from the system level specification to the bitstream generation neither for embedded system design
 nor for HPC.
-
-%PC => IA et Alain
-%Le paragraphe ci dessous n'a rien a faire dans la partie Economic et societal issue
-%Je le mets donc en commentaire
-
-%By using SOPC Builder~\cite{spoc-builder} from \altera, designers can select and
-%parameterize components from an extensive drop-down list of IP cores (I/O core, DSP,
-%processor,  bus core, ...) as well as incorporate their own IP.
-%Designers can then generate a synthesized netlist, simulation test bench and custom
-%software library that reflect the hardware configuration.
-%Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors and to
-%simulate the platform at a high design level (systemC). 
-%In addition, SOPC Builder is proprietary and only works together with \altera's Quartus compilation
-%tool to implement designs on \altera devices (Stratix, Arria, Cyclone).
-%PICO~\cite{pico} and CATAPULT-C~\cite{catapult-c} allow to synthesize
-%coprocessors from a C++ description.
-%Nevertheless, they can only deal with data dominated applications and they do not handle
-%the platform level.
-%Similarly, the System Generator for DSP~\cite{system-generateur-for-dsp} is a plug-in to
-%Simulink that enables designers to develop high-performance DSP systems for \xilinx FPGAs.
-%Designers can design and simulate a system using MATLAB and Simulink. The tool will then
-%automatically generate synthesizable Hardware Description Language (HDL) code mapped to
-%\xilinx pre-optimized macro-cells.
-%However, this tool targets only DSP based algorithms.
-%\\
-%Consequently, a designer developping an embedded system needs to master four different
-%design environments:
-%\begin{enumerate}
-%  \item a virtual prototyping environment such as SoCLib for system level exploration,
-%  \item an architecture compiler (such as SOPC Builder from \altera, or System generator
-%  from \xilinx) to define the hardware architecture,
-%  \item one or several HLS tools (such as PICO~\cite{pico} or CATAPULT-C~\cite{catapult-c}) for 
-%        coprocessor synthesis,
-%  \item and finally backend synthesis tools (such as Quartus or Synopsys) for the bit-stream generation.
-%\end{enumerate}
-%Furthermore, mixing these tools requires an important interfacing effort and this makes
-%the design process very complex and achievable only by designers skilled in many domains.
-
 \begin{center}\begin{minipage}{.9\linewidth}\textit{
 The aim of the COACH project is to integrate all these design steps into a single design framework
 and to allow \textbf{pure software} developpers to design embedded systems.
 }\end{minipage}\end{center}
-
-%PC => IA et Alain
-% le paragraphe suivant est coupé collé de la section suivante 2.2
-
-
-\parlf
+%
 The COACH project proposes an open-source framework for mapping multi-tasks software applications
 on Field Programmable Gate Array circuits (FPGA).