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1\anrdoc{Preciser:\begin{itemize}
2\item positionnement du projet par rapport au contexte developpe precedemment :
3          vis- a-vis des projets et recherches concurrents, complementaires ou
4          anterieurs, des brevets et standards...
5\item indiquer si le projet s'inscrit dans la continuite de projet(s) anterieurs
6          deja finances par l'ANR. Dans ce cas, presenter brievement les resultats acquis,
7\item positionnement du projet par rapport aux axes thematiques de l'appel a projets,
8\item positionnement du projet aux niveaux europeen et international.
9\end{itemize}}
10
11% Relevance of the proposal
12%The COACH proposal addresses directly the \emph{Embedded Systems} item of
13%the ARPEGE program.
14
15%PC => IA et ALain
16%J'aui déplacé le pargraphe ci dessous en conclusion de la section précédente 2.1
17
18%It aims to propose solutions to the societal/economical challenges by
19%providing SMEs novel design capabilities enabling them to increase their
20%design productivity with design exploration and synthesis methods that are placed on top
21%of the state-of-the-art methods.
22%This project proposes an open-source framework for mapping multi-tasks software applications
23%on Field Programmable Gate Array circuits (FPGA).
24%%%
25\subsubsection*{Positioning in regards with the economical and social context}
26COACH will contribute to build an open design and run-time
27environment, including communication middleware and tools to support
28developers in the production of embedded software, through all phases of the software life cycle,
29from requirements analysis down to deployment and maintenance.
30More specifically, COACH focuses on:
31\begin{itemize}
32\item High level methods and concepts (esp. Requirements and architectural level) for system
33design, development and integration, addressing complexity aspects and modularity.
34\item Open and modular design environments, enabling flexibility and extensibility by
35means of new or sector-specific tools and ensuring consistency and traceability along the
36development life cycle.
37\item Light/agile methodologies and adaptive workflow providing a dynamic and adaptive
38environment, suitable for co-operative and distributed development.
39\item Integration of the solutions and engines being developed into a state of the art SoC and system
40design flow, using the IP-XACT IEEE 1685 standard
41\end{itemize}
42The COACH results will contribute to strengthen Europe's competitive position by developing
43technologies and methodologies for product design, focusing (in compliance with the
44%scope of the above program) on technologies, engineering methodologies, novel tools,
45%methods which facilitate resource use efficiency. The approaches and tools to be developed
46%in COACH will enable new and emerging information technologies for the development,
47%methods which facilitate resource use efficiency. The COACH approaches and tools
48scope of the above program) on technologies, engineering methodologies, novel tools
49which facilitate resource use efficiency. The COACH approaches and tools
50will enable new and emerging information technologies for the development,
51manufacturing and integration of devices and related software into end-products.
52%%%
53\subsubsection*{Positioning and continuity with other projects}
54The COACH project will benefit from a number of previous recent projects:
55\begin{description}
56  \item[SOCLIB]
57    The SoCLib ANR platform (2007-2009) is an open infrastructure
58    that supports system level virtual prototyping of shared memory, multi-processors
59    architectures, and provides tools to map multi-tasks software application on these
60    architectures, for reliable performance evaluation.
61    The core of this platform is a library of SystemC simulation models for
62    general purpose IP cores.
63    It provides also embedded operating systems and software/hardware
64    communication middleware.
65  \item[ROMA] The ROMA ANR project (2007-2010) \cite{roma,RAFFIN:2010:INRIA-00539874:1}
66    involving IRISA (CAIRN team), LIRMM, CEA List, THOMSON France R\&D,
67    proposes to develop a reconfigurable processor, exhibiting high
68    silicon density and power efficiency, able to adapt its computing
69    structure to computation patterns that can be faster or more
70    power efficient.  %The ROMA project study a pipeline of
71    %evolved low-power coarse grain reconfigurable operators to avoid
72    %traditional overhead, in reconfigurable devices, related to the
73    %interconnection network. 
74        The project will borrow from the ROMA
75    ANR project and the ongoing joint INRIA-STMicro
76    Nano2012 project to adapt existing pattern extraction algorithms
77    and datapath merging techniques to ASIP synthesis.
78%    and datapath merging techniques to the synthesis of customized
79%    ASIP processors.
80  \item[TSAR]
81     The TSAR MEDEA+ project (2008-2010) involving BULL, THALES and \upmc targets the design of a
82%    The TSAR MEDEA+ project (2008-2010) targets the design of a
83    scalable, coherent shared memory, multi-cores processor architecture, and uses the SoCLib
84    platform for virtual prototyping. COACH will benefit from the synthesizable VHDL
85    models developed in the framework of TSAR (MIPS32 processor core, and RING interconnect).
86  \item[BioWic]
87    On the HPC application side, we also hope to benefit from the experience in
88    hardware acceleration of bioinformatic algorithms/workfows gathered by the
89    CAIRN group in the context of the ANR BioWic project (2009-2011), so as to
90    be able to validate the framework on real-life HPC applications.
91
92  \item[SoCket] 
93    The design flow defined in this project targets the design of critical embedded systems.
94    It covers important steps as system architecture exploration, and the definition of virtual
95    prototypes at different levels of abstraction to support early embedded software development,
96    verification of hardware blocks, and preparation of certification activities.
97    COACH solutions and engines will be specified to be integrated into this standard flow.
98    MDS, Thales TRT, TIMA are already collaborating in this project.
99
100  \item[HOSPI] 
101     The objective of this project (with TIMA and MDS) was to define innovative methods, and implement the associated tools, to ease
102     the mapping of data-streaming applications on heterogeneous platforms. COACH will use the abstracted description
103     format based on IP-XACT for hardware platforms and the results concerning the integration of code generators into a standard design flow.
104
105  \item[SoftSoC] 
106     TIMA and MDS are involved in this project, which aims at the standard definition and generation of Hardware Dependent Software layers of a system.
107     Crucial extensions of the IP-XACT standard will be reused from this project, as well as code generation techniques based on them. 
108
109\end{description}
110%%%
111The partners involved in the COACH project have a well established expertise
112in the following domains:
113\begin{itemize}
114  \item 
115    In the field of High Level Synthesis (HLS), the project
116    leverages on know-how acquired over the last 15 years with the GAUT~\cite{gaut08} project
117    developed by the \ubs laboratory, and with the UGH~\cite{ugh08} project developed
118    by the \upmc and \tima laboratories.
119  \item
120    Regarding system level architecture, the project is based on the know-how
121    acquired by \upmc and \tima in the framework of various projects 
122    in the field of communication architectures for shared memory multi-processors systems
123    (COSY~\cite{cosy}, DISYDENT~\cite{disydent05} or DSPIN~\cite{dspin08} of MEDEA-MESA).
124    As an example, the DSPIN project is now used in the TSAR project.
125  \item
126    Regarding Application Specific Instruction Processor (ASIP) design, the
127    CAIRN group at INRIA Rennes -- Bretagne Atlantique benefits from several years of
128    expertise in the domain of retargetable compiler
129    (Armor/Calife~\cite{CODES99} since 1996, and the Gecos
130    compilers~\cite{ASAP05} since 2002).
131  \item
132    In the field of compilers, the \lip Compsys group was founded in 2002
133    by several senior researchers with experience in
134    high performance computing and automatic parallelization. They have been
135    among the initiators of the polyhedral model, a theory which serve to
136    unify many parallelism detection and exploitation techniques for regular
137    programs. It is expected that the techniques developed by \lip for
138    parallelism detection, scheduling \cite{Feau:92aa,Feau:92bb},
139    process construction \cite{Feau:96} and memory management \cite{bee}
140    will be very useful as a front-end for HLS tools.
141  \item
142    Regarding industrial flow integration \mds will bring its strong expertise
143    in IEEE 1685 (IP-XACT) standard. The \mds team is involved and contributes actively
144    to it since 2003 and the Magillem tool suite is used for its validation. Magillem is used in
145    industrial production flows of ST, NXP, TI, Qualcomm, and system integrators like Thales,
146    Astrium, Thomson, etc. This guarantees a strong alignement on customers needs and enhanced results exploitation.
147
148\end{itemize}
149%%%
150\subsubsection*{Relevance to the call axis}
151This project answer to the global statement of the call "INGENIERIE NUMERIQUE ET SECURITE (INS)" by proposing
152methods and tools for the design of application to be run on platforms of the next generation.
153Improvements can be expected for productivity,
154time-to-market (automation and code generation) and reliability (management of high level specifications down to implementation).
155In this call, the COACH project totally fulfills the objectives of the axis 2 "METHODES,
156OUTILS ET TECHNOLOGIES POUR LES SYSTEMES EMBARQUES".
157COACH will address new embedded systems architectures by allowing the design of
158Multi-Core Systems-on-Chip (possibly heterogeneous) on FPGA according to the design
159constraints and objectives (real-time, low-power). It will permit designing  complex SoC
160based on IP cores (memory, peripherals...),
161running Embedded Software, as well as an Operating System with associated middleware and
162API and using automatically generated hardware accelerators. It will also permit to use
163efficiently different dynamic system management techniques and re-configuration mechanisms.
164The results will be tailored in order to be integrated in standard design flow of critical systems.
165\\
166COACH will address High-Performance Computing (HPC) by helping designers to accelerate an
167application running on a PC.
168By providing tools that translate high level language programs to FPGA
169configurations, COACH will allow to easily migrate critical parts into an FPGA plugged to the
170PC bus (through a communication link like PCI/X).
171\parlf
172The COACH project has been also shaped to answer to the axis 5 "USAGES".
173COACH will address robotic and control applications by
174allowing to design complex systems based on MPSoC architecture.
175Like in the consumer electronics domain, future control applications
176will employ more and more SoC for safety and security applications.
177Application domains for such systems are for example automotive
178or avionics domains (e.g. collision-detection, intelligent navigation...).
179Manufacturing technology will also increasingly need high-end vision analysis and high-speed
180robot control.
181%
182The results of the COACH project will help users to build cryptographic secure systems implemented in
183in a combination of hardware and software in an effective way, substantially enhancing the
184productivity of the field, improving the
185quality and reducing the design time and the cost of synthesised cryptographic devices.
186%
187COACH will contribute to enhance the safety in design of critical system for two main reasons:
188\begin{itemize}
189  \item by providing a way to automate the mapping of application onto MPSoC
190  architecture; code generators of the tool chain will be subject to
191  certification.
192  \item by relaying on design flow defined by SoCKET, which is dedicated to
193  safety of critical systems, COACH will benefit from features related to
194  requirements traceability.
195\end{itemize}
196%
197\subsubsection*{European and international positioning}
198%
199Finally, it is worth noting that this project covers priorities defined by the commission
200experts in the field of Information Technologies Society (IST) for Embedded
201Systems: \textit{ $<<$Concepts, methods and tools for designing systems dealing with systems complexity
202and allowing to apply efficiently applications and various products on embedded platforms,
203considering resources constraints (delays, power, memory, etc.), security and quality
204services$>>$}.
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