source: anr/task-2.tex @ 172

Last change on this file since 172 was 155, checked in by coach, 15 years ago

INRIA/COMPSYS -> LIP

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1\begin{taskinfo}
2\let\UPMC\leader
3\let\IRISA\enable
4\let\TIMA\enable
5\let\XILINX\enable
6\let\UBS\enable
7\end{taskinfo}
8%
9\begin{objectif}
10This task deals with the prototyping and the generation of FPGA-SoC digital systems.
11Its is described on figure~\ref{archi-csg}.
12Its objective is to allow the system designer to explore the system space design by
13quickly prototyping and then to generate automatically the FPGA-SoC system.
14This task consists of
15\begin{itemize}
16\item the development of all the missing components (SytemC models and/or synthesizable VHDL models
17of the IP-cores),
18\item the configuration and the development of drivers of the operating systems (Board Support Package, HAL),
19\item the CSG software that generates the SystemC simulators for prototyping and the FPGA-SoC system
20including its bitstream and software executable code,
21\item the specification of enhanced communication schemes and their sofware and hardware implementations.
22\end{itemize}
23This task being based on the SocLib platform, a first release will be delivered at $T0+12$
24to allow the demonstrators to start working.
25This release will include the standard communication schemes (base on SocLib MWMR component)
26and support the neutral architectural template for prototyping and hardware generation.
27\end{objectif}
28%
29\begin{workpackage}
30\subtask This \ST corresponds to the COACH System Generator (CSG) software.
31    \begin{livrable}
32    \itemV{0}{12}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgCoachArch}
33        The first software release of the CSG tool that will allow demonstrators to start
34        working by using the neutral architectural template.
35    \itemV{12}{18}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgPrototypingOnly}
36        The second release of CSG supports the \xilinx and \altera architectural
37        templates and the enhanced communication system, but only for SystemC prototyping.
38        This release integrates a first integration of HLS tools.
39    \itemV{18}{24}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgAllArch}
40        This milestone extends CSG (\csgPrototypingOnly) to
41        FPGA-SoC generation for the \xilinx and \altera architectural template.
42    \itemL{24}{36}{x}{\Supmc}{CSG}{6:5.5:5.5}
43        Final release of CSG.
44    \end{livrable}
45\subtask This \ST deals with the components of the architectural templates.
46    \\
47    For the neutral architectural template, it consists of the development of the VHDL
48    synthesizable description of the missing communication components (MWMR)
49        in order to support the process network communication model.
50    Notice that the SystemC models
51    comes from the SocLib ANR project, the processor with its cache comes from the TSAR
52    ANR project.
53    \\
54    For the \xilinx and \altera architectural templates, we use the \xilinx and \altera IPs (NIOS, Microblaze, memories, busses...).
55    \begin{livrable}
56    \itemL{0}{12}{h}{\Supmc}{neutral architecture}{1:0:0}
57        \setMacroInAuxFile{csgCoachArchTempl}
58        The VHDL synthesizable descriptions of the SocLib MWMR, TokenRing components.
59    \itemL{12}{15}{d}{\Sxilinx}{\xilinx RTL optimisation (2)}{0:2:0}
60       This deliverable consists in optimizing the VHDL descriptions of the components of
61       the neutral architectural template (deliverable \novers{\csgCoachArchTempl}) to the
62       \xilinx RTL synthesis tools.
63       \upmc will provide the VHDL descriptions, \xilinx will provide back a documentation
64       listing that proposes VHDL generation enhancements.
65    \itemV{6}{18}{x}{\Stima}{\xilinx architecture}
66        \setMacroInAuxFile{csgXilinxSystemC}
67        The SystemC simulation module of the MWMR component with a PLB bus interface plus
68        the SystemC modules of the components of the \xilinx architectural template
69        currently not available in the SocLib component library.
70    \itemL{18}{24}{h}{\Stima}{\xilinx architecture}{9:9:0}
71        The synthesizable VHDL description of the MWMR component corresponding to the
72        SystemC module of the former deliverable (\csgXilinxSystemC).
73    \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimisation (3)}{0:0:1.5}
74       This deliverable consists in optimizing the MWMR VHDL description (deliverable
75       \novers{\csgXilinxSystemC}) of the \xilinx architectural template.
76       \tima will provide MWMR VHDL description, \xilinx will provide back a documentation
77       listing that proposes VHDL generation enhancements.
78    \itemV{6}{18}{x}{\Sirisa}{\altera architecture}
79        \setMacroInAuxFile{csgAlteraSystemC}
80        The SystemC simulation module of the MWMR component with an AVALON bus interface plus
81        the SystemC modules of the components of the \altera architectural template
82        currently not available in the SocLib component library.
83    \itemL{18}{24}{h}{\Sirisa}{\altera architecture}{6:6:0}
84        The synthesizable VHDL description of the MWMR component corresponding to the
85        SystemC module of the former deliverable (\csgAlteraSystemC);
86    \itemV{6}{12}{d}{\Subs}{UBS communication adapter}
87       \setMacroInAuxFile{gautCOMMoptimization}
88       Specification of an optimized communication adapter (space and time) component to handle data interleaving.
89       This evolution aims to solve out of order communication weakness of the classical MWMR.
90    \itemV{12}{24}{x}{\Subs}{UBS communication adapter}
91       First release of the tool that generates the VHDL description of the optimized communication adapter
92       and its corresponding SystemC module.
93    \itemL{24}{30}{x}{\Subs}{UBS communication adapter}{0:0:0}
94       Final release of the tool that generates the VHDL description of the optimized
95       communication adapter and its corresponding SystemC module (\gautCOMMoptimization).
96    \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimisation (4)}{0:0:1.5}
97       This deliverable consists in optimizing the communication adapter VHDL description (deliverable
98       \novers{\gautCOMMoptimization}).
99       \ubs will provide communication adapter VHDL description, \xilinx will provide back a documentation
100       listing that proposes VHDL generation enhancements.
101    \end{livrable}
102\subtask This \ST consists of the configuration of the SocLib MUTEKH and DNA operating
103    system and the development of drivers for the hardware architectural templates
104    and enhanced communication schemes defined in \novers{\specCsgManual} deliverable.
105    For the \altera and \xilinx architectural templates, the OSs must also be ported on
106    the NIOS2 and MICROBLAZE processors.
107    \begin{livrable}
108    \itemV{6}{8}{x}{\Supmc}{MUTEKH OS}
109        The drivers required for the first CSG milestone (deliverable \csgCoachArch).
110    \itemV{8}{18}{x}{\Supmc}{MUTEKH 0S}
111        The drivers required for the second CSG milestone ({\csgPrototypingOnly}).
112    \itemL{18}{33}{x}{\Supmc}{MUTEKH OS}{1:1:2}
113        Maintenance work.
114    \itemL{6}{18}{x}{\Supmc}{Port of MUTEKH OS}{1.0:1:0}
115        Porting of MUTEKH OS on the NIOS2 and MICROBLAZE processors.
116    \itemV{6}{8}{x}{\Stima}{DNA OS}
117        The drivers required for the first CSG milestone (deliverable \csgCoachArch).
118    \itemV{8}{18}{x}{\Stima}{DNA 0S}
119        The drivers required for the second CSG milestone ({\csgPrototypingOnly}).
120    \itemL{18}{33}{x}{\Stima}{DNA OS}{6:3:2}
121        Maintenance work.
122    \itemL{6}{18}{x}{\Stima}{Port of DNA OS}{3:1:0}
123        Porting of DNA OS on the NIOS2 and MICROBLAZE processors.
124    \end{livrable}
125\end{workpackage}
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