1 | \begin{taskinfo} |
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2 | \let\UPMC\leader |
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3 | \let\IRISA\enable |
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4 | \let\TIMA\ensable |
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5 | \end{taskinfo} |
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6 | % |
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7 | \begin{objectif} |
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8 | This task relies to the prototyping and the generation of FPGA-SoC digital systems. |
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9 | Its is described on figure~\ref{archi-csg}. |
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10 | Its objective is to allow the system designer to explore the system space design by |
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11 | quickly prototyping and then to generate automatically the FPGA-SoC system. |
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12 | This task consists of |
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13 | \begin{itemize} |
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14 | \item the development of all the missing components (SytemC model and/or synthesizable VHDL description), |
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15 | \item the configuration and the development of drivers of the operating systems, |
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16 | \item the CSG software that generates the simulators for prototiping and the FPGA-SoC system, |
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17 | \item the specification of enhanced communication schemes and their sofware and hardware implementation. |
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18 | \end{itemize} |
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19 | This task being based on the SocLib platform, a first release will be delivrable at $T0+12$ |
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20 | to allow the demonstrators to start working. |
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21 | This release will include the standard communication schemes (base on SocLib MWMR component) |
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22 | and support the COACH architectural template for prototyping and hardware generation. |
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23 | \end{objectif} |
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24 | % |
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25 | \begin{workpackage}{D2} |
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26 | \item This \ST corresponds to the Coach System Generator (CSG) software. |
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27 | \begin{livrable} |
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28 | \item{V1}{0}{12}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgCoachArch} |
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29 | The first milestone that will allow demonstrators to start working using the COACH |
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30 | hardware architecture template. |
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31 | \item{V2}{12}{18}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgPrototypingOnly} |
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32 | This milestone adds to CSG the support to the XILINX and ALTERA architectural |
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33 | templates and to the enhanced communication system. |
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34 | In this milestone only the SystemC prototyping will be supported for the XILINX |
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35 | and ALTERA architectural template. |
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36 | HAS is available. |
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37 | \item{V3}{18}{24}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgAllArch} |
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38 | This milestone extends CSG (\csgPrototypingOnly) to |
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39 | FPGA-SoC generation for the XILINX and ALTERA architectural template. |
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40 | \item{VF}{24}{36}{x}{\Supmc}{CSG} Maintenance work of CSG. |
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41 | \end{livrable} |
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42 | \item This \ST relies to the components of the architectural template. |
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43 | \\ |
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44 | For the COACH architectural template, it consists of the devlopment of the VHDL |
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45 | synthesizable description of the missing components. Notice that the SystemC models |
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46 | comes from the SocLib ANR project, the processor with its cache comes from the TSAR |
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47 | ANR project. |
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48 | \\ |
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49 | For the XILINX and ALTERA architectural template, we use the XILINX and ALTERA IPs. |
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50 | The component that miss is the MWMR used for commucation between the task of the |
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51 | application. |
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52 | \begin{livrable} |
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53 | \item{}{0}{12}{h}{\Supmc}{COACH architecture} The VHDL synthesizable descriptions |
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54 | of the SocLib MWMR, TokenRing components. |
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55 | \item{V1}{6}{18}{x}{\Stima}{XILINX architecture} |
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56 | \setMacroInAuxFile{csgXilinxSystemC} |
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57 | The SystemC simulation module of the MWMR component with a PLB bus interface plus |
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58 | the SystemC modules of the components of the XILINX architectural template |
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59 | not available in the SocLib component library. |
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60 | \item{VF}{18}{24}{h}{\Stima}{XILINX architecture} |
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61 | The synthesizable VHDL description of the MWMR component corresponding to the |
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62 | SystemC module of the former delivrable (\csgXilinxSystemC). |
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63 | \item{V1}{6}{18}{x}{\Sirisa}{ALTERA architecture} |
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64 | \setMacroInAuxFile{csgAlteraSystemC} |
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65 | The SystemC simulation module of the MWMR component with a AVALON bus interface plus |
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66 | the SystemC modules of the components of the ALTERA architectural template |
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67 | not available in the SocLib component library. |
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68 | \item{VF}{18}{24}{h}{\Sirisa}{ALTERA architecture} |
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69 | The synthesizable VHDL description of the MWMR component corresponding to the |
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70 | SystemC module of the former delivrable (\csgAlteraSystemC); |
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71 | \end{livrable} |
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72 | \item This \ST consists of the configuration of the SocLib MUTEK and DNA operating |
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73 | system and the development of drivers for the hardware architectural templates |
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74 | and enhanced communication schemes defined in \novers{\specCsgManual} delivrable. |
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75 | For the ALTERA and XILINX architectural template, the OSs must also be ported on |
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76 | the NIOS2 and MICROBLAZE processors. |
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77 | \begin{livrable} |
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78 | \item{V1}{6}{8}{x}{\Supmc}{MUTEK OS} The drivers required for the first CSG |
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79 | milestone (delivrable \csgCoachArch). |
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80 | \item{V2}{8}{18}{x}{\Supmc}{MUTEK 0S} The drivers required for the |
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81 | second CSG milestone ({\csgPrototypingOnly}). |
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82 | \item{VF}{18}{33}{x}{\Supmc}{MUTEK OS} Maintenance work. |
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83 | \item{}{6}{18}{x}{\upmc}{Port of MUTEK OS} |
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84 | Port of MUTEK OS on the NIOS2 and MICROBLAZE processors. |
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85 | \item{V1}{6}{8}{x}{\tima}{DNA OS} The drivers required for the first CSG |
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86 | milestone (delivrable \csgCoachArch). |
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87 | \item{V2}{8}{18}{x}{\Stima}{DNA 0S} The drivers required for the |
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88 | second CSG milestone ({\csgPrototypingOnly}). |
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89 | \item{VF}{18}{33}{x}{\Stima}{DNA OS} Maintenance work. |
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90 | \item{}{6}{18}{x}{\tima}{Port of DNA OS} |
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91 | Port of MUTEK OS on the NIOS2 and MICROBLAZE processors. |
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92 | \end{livrable} |
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93 | % moved in task 1 |
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94 | %\item This \ST relies to definition and implementation of the enhanced communication |
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95 | % schemes usable in the definition of communicante task graph. |
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96 | % \begin{livrable} |
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97 | % \item{}{0}{6}{d}{\Stima}{CSG user manual} A document that describes the CSG task |
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98 | % graph inputs (task graph, task description, communication schemes). |
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99 | % \end{livrable} |
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100 | %\item This \ST relies to implementation of the MWMR component for the Xilinx and Altera |
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101 | % architectural template. |
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102 | % \begin{livrable} |
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103 | % \item{}{0}{18}{x}{\Stima}{MWMR Altera} The VHDL synthesizable description and |
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104 | % SystemC model of the MWMR with a PLB bus interface. |
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105 | % \item{}{0}{18}{x}{\Sirisa}{MWMR Altera} The VHDL synthesizable description and |
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106 | % SystemC model of the MWMR with an AVALON bus interface. |
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107 | % \end{livrable} |
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108 | % FIXME:CITI |
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109 | \end{workpackage} |
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