Changeset 38 for anr/task-2.tex
- Timestamp:
- Jan 19, 2010, 11:01:35 AM (15 years ago)
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anr/task-2.tex
r36 r38 15 15 \item the configuration and the development of drivers of the operating systems, 16 16 \item the CSG software that generates the simulators for prototiping and the FPGA-SoC system, 17 \item the specification of enhanced communication schem s and their sofware and hardware implementation.17 \item the specification of enhanced communication schemes and their sofware and hardware implementation. 18 18 \end{itemize} 19 19 This task being based on the SocLib platform, a first release will be delivrable at $T0+12$ 20 20 to allow the demonstrators to start working. 21 This release will include the standard communication schem s (base on SocLib MWMR component)21 This release will include the standard communication schemes (base on SocLib MWMR component) 22 22 and support the COACH architectural template for prototyping and hardware generation. 23 23 \end{objectif} … … 72 72 \item This \ST consists of the configuration of the SocLib MUTEK and DNA operating 73 73 system and the development of drivers for the hardware architectural templates 74 and enhanced communication schem s defined in \novers{\specCsgManual} delivrable.74 and enhanced communication schemes defined in \novers{\specCsgManual} delivrable. 75 75 For the ALTERA and XILINX architectural template, the OSs must also be ported on 76 76 the NIOS2 and MICROBLAZE processors. … … 93 93 % moved in task 1 94 94 %\item This \ST relies to definition and implementation of the enhanced communication 95 % schem s usable in the definition of communicante task graph.95 % schemes usable in the definition of communicante task graph. 96 96 % \begin{livrable} 97 97 % \item{}{0}{6}{d}{\Stima}{CSG user manual} A document that describes the CSG task 98 % graph inputs (task graph, task description, communication schem s).98 % graph inputs (task graph, task description, communication schemes). 99 99 % \end{livrable} 100 100 %\item This \ST relies to implementation of the MWMR component for the Xilinx and Altera
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