1 | \begin{taskinfo} |
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2 | \let\UPMC\leader |
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3 | \let\IRISA\enable |
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4 | \let\TIMA\enable |
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5 | \let\XILINX\enable |
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6 | \end{taskinfo} |
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7 | % |
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8 | \begin{objectif} |
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9 | This task deals with the prototyping and the generation of FPGA-SoC digital systems. |
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10 | Its is described on figure~\ref{archi-csg}. |
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11 | Its objective is to allow the system designer to explore the system space design by |
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12 | quickly prototyping and then to generate automatically the FPGA-SoC system. |
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13 | This task consists of |
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14 | \begin{itemize} |
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15 | \item the development of all the missing components (SytemC models and/or synthesizable VHDL models |
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16 | of the IP-cores), |
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17 | \item the configuration and the development of drivers \mustbecompleted{FIXME:: driver de quoi ???} |
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18 | of the operating systems, |
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19 | \item the CSG software that generates the SystemC simulators for prototyping and the synthesizable description |
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20 | of the FPGA-SoC system (i.e. its bitstream), \mustbecompleted{FIXME:: VHDL ou bitstream ???} |
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21 | \item the specification of enhanced communication schemes and their sofware and hardware implementations. |
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22 | \end{itemize} |
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23 | This task being based on the SocLib platform, a first release will be delivrable at $T0+12$ |
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24 | to allow the demonstrators to start working. |
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25 | This release will include the standard communication schemes (base on SocLib MWMR component) |
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26 | and support the COACH architectural template for prototyping and hardware generation. |
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27 | \end{objectif} |
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28 | % |
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29 | \begin{workpackage} |
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30 | \item This \ST corresponds to the Coach System Generator (CSG) software. |
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31 | \begin{livrable} |
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32 | \itemV{0}{12}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgCoachArch} |
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33 | The first software release of the CSG tool that will allow demonstrators to start working by using the COACH |
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34 | hardware architecture template. |
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35 | \itemV{12}{18}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgPrototypingOnly} |
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36 | This milestone adds to CSG the support to the XILINX and ALTERA architectural |
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37 | templates and to the enhanced communication system. |
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38 | In this milestone only the SystemC prototyping will be supported for the XILINX |
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39 | and ALTERA architectural template. |
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40 | HAS is available. \mustbecompleted{FIXME:: ca veut dire ???} |
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41 | \itemV{18}{24}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgAllArch} |
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42 | This milestone extends CSG (\csgPrototypingOnly) to |
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43 | FPGA-SoC generation for the XILINX and ALTERA architectural template. |
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44 | \itemL{24}{36}{x}{\Supmc}{CSG}{6:6:6} |
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45 | Maintenance work of CSG. |
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46 | \end{livrable} |
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47 | \item This \ST deals with the components of the architectural templates. |
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48 | \\ |
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49 | For the COACH architectural template, it consists of the devlopment of the VHDL |
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50 | synthesizable description of the missing components. \mustbecompleted{FIXME :: pas clair missing components} |
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51 | Notice that the SystemC models |
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52 | comes from the SocLib ANR project, the processor with its cache comes from the TSAR |
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53 | ANR project. |
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54 | \\ |
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55 | For the XILINX and ALTERA architectural templates, we use the XILINX and ALTERA IPs (NIOS, Microblaze, memories, busses...). |
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56 | The missing component is the MWMR used for communication between the tasks of the |
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57 | application. |
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58 | \begin{livrable} |
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59 | \itemL{0}{12}{h}{\Supmc}{COACH architecture}{1:0:0} |
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60 | \setMacroInAuxFile{csgCoachArchTempl} |
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61 | The VHDL synthesizable descriptions of the SocLib MWMR, TokenRing components. |
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62 | \itemL{12}{15}{d}{\Sxilinx}{\xilinx RTL optimisation (2)}{0:2:0} |
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63 | This deliverable consists in optimizing the VHDL descriptions of the components of |
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64 | the COACH architectural template (deliverable \novers{\csgCoachArchTempl}) to the |
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65 | \xilinx RTL synthesis tools. |
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66 | \upmc will provide the VHDL descriptions, \xilinx will provide back a documentation |
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67 | listing that proposes VHDL generation enhancements. |
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68 | \itemV{6}{18}{x}{\Stima}{XILINX architecture} |
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69 | \setMacroInAuxFile{csgXilinxSystemC} |
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70 | The SystemC simulation module of the MWMR component with a PLB bus interface plus |
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71 | the SystemC modules of the components of the XILINX architectural template |
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72 | currently not available in the SocLib component library. |
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73 | \itemL{18}{24}{h}{\Stima}{XILINX architecture}{9:9:0} |
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74 | The synthesizable VHDL description of the MWMR component corresponding to the |
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75 | SystemC module of the former delivrable (\csgXilinxSystemC). |
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76 | \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimisation (3)}{0:0:2} |
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77 | This deliverable consists in optimizing the MWMR VHDL description (deliverable |
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78 | \novers{\csgXilinxSystemC}) of the \xilinx architectural template. |
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79 | \tima will provide MWMR VHDL description, \xilinx will provide back a documentation |
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80 | listing that proposes VHDL generation enhancements. |
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81 | \itemV{6}{18}{x}{\Sirisa}{ALTERA architecture} |
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82 | \setMacroInAuxFile{csgAlteraSystemC} |
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83 | The SystemC simulation module of the MWMR component with an AVALON bus interface plus |
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84 | the SystemC modules of the components of the ALTERA architectural template |
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85 | currently not available in the SocLib component library. |
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86 | \itemL{18}{24}{h}{\Sirisa}{ALTERA architecture}{0:0:0} |
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87 | The synthesizable VHDL description of the MWMR component corresponding to the |
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88 | SystemC module of the former delivrable (\csgAlteraSystemC); |
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89 | \itemV{6}{12}{d}{\Subs}{UBS communication adapter} |
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90 | \setMacroInAuxFile{gautCOMMoptimization} |
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91 | Specification of an optimized communication adapter (space and time) component to handle data interleaving. |
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92 | This evolution aims to solve out of order communication weakness of the classical MWMR. |
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93 | \itemV{12}{24}{x}{\Subs}{UBS communication adapter} |
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94 | First release of the tool that generates the VHDL description of the optimized communication adapter |
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95 | and its corresponding SystemC module. |
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96 | \itemL{24}{30}{x}{\Subs}{UBS communication adapter}{0:0:0} |
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97 | Final release of the tool that generates the VHDL description of the optimized communication adapter |
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98 | and its corresponding SystemC module (\gautCOMMoptimization). |
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99 | \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimisation (4)}{0:0:2} |
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100 | This deliverable consists in optimizing the communication adapter VHDL description (deliverable |
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101 | \novers{\gautCOMMoptimization}). |
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102 | \ubs will provide communication adapter VHDL description, \xilinx will provide back a documentation |
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103 | listing that proposes VHDL generation enhancements. |
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104 | \end{livrable} |
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105 | \item This \ST consists of the configuration of the SocLib MUTEK and DNA operating |
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106 | system and the development of drivers for the hardware architectural templates |
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107 | and enhanced communication schemes defined in \novers{\specCsgManual} delivrable. |
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108 | For the ALTERA and XILINX architectural templates, the OSs must also be ported on |
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109 | the NIOS2 and MICROBLAZE processors. |
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110 | \begin{livrable} |
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111 | \itemV{6}{8}{x}{\Supmc}{MUTEK OS} |
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112 | The drivers \mustbecompleted{FIXME :: ???} |
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113 | required for the first CSG milestone (delivrable \csgCoachArch). |
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114 | \itemV{8}{18}{x}{\Supmc}{MUTEK 0S} |
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115 | The drivers required for the second CSG milestone ({\csgPrototypingOnly}). |
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116 | \itemL{18}{33}{x}{\Supmc}{MUTEK OS}{1:1:2} |
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117 | Maintenance work. |
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118 | \itemL{6}{18}{x}{\Supmc}{Port of MUTEK OS}{1.0:1:0} |
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119 | Porting of MUTEK OS on the NIOS2 and MICROBLAZE processors. |
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120 | \itemV{6}{8}{x}{\Stima}{DNA OS} |
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121 | The drivers required for the first CSG milestone (delivrable \csgCoachArch). |
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122 | \itemV{8}{18}{x}{\Stima}{DNA 0S} |
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123 | The drivers required for the second CSG milestone ({\csgPrototypingOnly}). |
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124 | \itemL{18}{33}{x}{\Stima}{DNA OS}{6:3:2} |
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125 | Maintenance work. |
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126 | \itemL{6}{18}{x}{\Stima}{Port of DNA OS}{3:1:0} |
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127 | Porting of DNA OS on the NIOS2 and MICROBLAZE processors. |
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128 | \end{livrable} |
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129 | \end{workpackage} |
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