Changeset 113 for anr/task-2.tex

Timestamp:

Feb 8, 2010, 11:40:38 PM (14 years ago)

Author:

coach

Message:

IA: updated pour XILINX

File:

• anr/task-2.tex (modified) (4 diffs)

anr/task-2.tex

@@ -3 +3 @@
 \let\IRISA\enable
 \let\TIMA\enable
+\let\XILINX\enable
 \end{taskinfo}
 %
@@ -57 +58 @@
     \begin{livrable}
     \itemL{0}{12}{h}{\Supmc}{COACH architecture}{1:0:0}
+        \setMacroInAuxFile{csgCoachArchTempl}
         The VHDL synthesizable descriptions of the SocLib MWMR, TokenRing components.
+    \itemL{12}{15}{d}{\Sxilinx}{\xilinx RTL optimisation (2)}{0:2:0}
+       This deliverable consists in optimizing the VHDL descriptions of the components of
+       the COACH architectural template (deliverable \novers{\csgCoachArchTempl}) to the
+       \xilinx RTL synthesis tools.
+       \upmc will provide the VHDL descriptions, \xilinx will provide back a documentation
+       listing that proposes VHDL generation enhancements.
     \itemV{6}{18}{x}{\Stima}{XILINX architecture}
         \setMacroInAuxFile{csgXilinxSystemC}
@@ -66 +74 @@
         The synthesizable VHDL description of the MWMR component corresponding to the
         SystemC module of the former delivrable (\csgXilinxSystemC).
+    \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimisation (3)}{0:0:2}
+       This deliverable consists in optimizing the MWMR VHDL description (deliverable
+       \novers{\csgXilinxSystemC}) of the \xilinx architectural template.
+       \tima will provide MWMR VHDL description, \xilinx will provide back a documentation
+       listing that proposes VHDL generation enhancements.
     \itemV{6}{18}{x}{\Sirisa}{ALTERA architecture}
         \setMacroInAuxFile{csgAlteraSystemC}
@@ -84 +97 @@
        Final release of the tool that generates the VHDL description of the optimized communication adapter
        and its corresponding SystemC module (\gautCOMMoptimization).
+    \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimisation (4)}{0:0:2}
+       This deliverable consists in optimizing the communication adapter VHDL description (deliverable
+       \novers{\gautCOMMoptimization}).
+       \ubs will provide communication adapter VHDL description, \xilinx will provide back a documentation
+       listing that proposes VHDL generation enhancements.
     \end{livrable}
 \item This \ST consists of the configuration of the SocLib MUTEK and DNA operating