source: anr/task-2.tex @ 279

\begin{taskinfo}
\let\UPMC\leader
\let\IRISA\enable
\let\TIMA\enable
\let\XILINX\enable
\let\UBS\enable
\end{taskinfo}
%
\begin{objectif}
This task deals with the prototyping and the generation of FPGA-SoC digital systems.
Its is described on figure~\ref{archi-csg}.
Its objective is to allow the system designer to explore the design space by
quickly prototyping and then to automatically generate the FPGA-SoC systems.
This task consists of:
\begin{itemize}
\item The development of the synthesizable models required for the connection of
the coprocessors on the platform bus (2 bridges).
\item The configuration and the development of drivers of the operating systems (Board Support Package, HAL),
\item The CSG software that generates the SystemC simulators for prototyping and the FPGA-SoC system
including its bitstream and software executable code,
\end{itemize}
A first release will be delivered at $T0+12$ to allow the demonstrators to start working.
This release will include the standard communication schemes based on SoCLib MWMR component
and support the neutral architectural template for prototyping and hardware generation.
\end{objectif}
%
\begin{workpackage}
\subtask{Bridge implementation}
    This \ST deals with the development of the synthesizable models required for the connection of
    the coprocessors on the platform bus).
    \begin{livrable}
    \itemL{9}{18}{h}{\Stima}{HPC hardware \xilinx}{3:9:0}
        \setMacroInAuxFile{hpcPlbBridge}
        The synthesizable VHDL description of a PLB/VCI bridge.
    \itemL{9}{18}{h}{\Supmc}{HPC hardware \altera}{1:2:0}
        \setMacroInAuxFile{hpcAvalonBridge}
        The synthesizable VHDL description of an AVALON/VCI bridge.
    \end{livrable}
\subtask{OS setup} This \ST consists of the configuration of the SocLib DNA operating
    system and the development of drivers for the hardware architectural templates.
    For the \altera and \xilinx architectural templates, the OSs must also be ported on
    the NIOS2 and MICROBLAZE processors.
    \begin{livrable}
%IVG    \itemV{6}{8}{x}{\Supmc}{MUTEKH OS}
%IVG        The drivers required for the first CSG milestone (deliverable \csgCoachArch).
%IVG    \itemV{8}{18}{x}{\Supmc}{MUTEKH 0S drivers}
%IVG        The drivers required for the second CSG milestone ({\csgPrototypingOnly}).
%IVG    \itemL{18}{33}{x}{\Supmc}{MUTEKH OS drivers}{1:1:2}
%IVG        Final release of the MUTEKH OS drivers.
%IVG    \itemL{6}{18}{x}{\Supmc}{Porting of MUTEKH OS}{1.0:1:0}
%IVG        Porting of MUTEKH OS on the NIOS2 and MICROBLAZE processors.
    \itemV{6}{8}{x}{\Stima}{DNA OS}
        The drivers required for the first CSG milestone.
    \itemV{8}{18}{x}{\Stima}{DNA 0S}
        The drivers required for the second CSG milestone.
    \itemL{18}{33}{x}{\Stima}{DNA OS drivers}{6:3:2}
        Final release of the DNA OS drivers.
    \itemL{6}{18}{x}{\Stima}{Porting of DNA OS}{3:1:0}
        Porting of DNA OS on the NIOS2 and MICROBLAZE processors.
    \end{livrable}
%
\subtask{Implementation of CSG} This \ST corresponds to the COACH System Generator (CSG) software.
    \begin{livrable}
    \itemV{0}{12}{x}{\Supmc}{CSG tool}
        The first software release of the CSG tool that will allow demonstrators to start
        working by using the neutral architectural template only for SystemC.
    \itemV{12}{18}{x}{\Supmc}{CSG}
        The second release of CSG integrates the VHDL driver for the neutral
        architectural template, and an integration of an HLS tools
        but only for SystemC prototyping.
    \itemV{18}{24}{x}{\Supmc}{CSG}
        This release extends CSG to FPGA-SoC generation for the \xilinx and \altera architectural template.
    \itemL{24}{36}{x}{\Supmc}{CSG tool}{6:5.5:5.5} \setMacroInAuxFile{csgImplementation}
        Final release of CSG enhanced by the demonstrator's feedback.
    \end{livrable}
\end{workpackage}