Changeset 278 for anr/task-2.tex


Ignore:
Timestamp:
Nov 24, 2010, 12:14:38 AM (14 years ago)
Author:
coach
Message:

Reduced the task number. Suppressed xilinx, navtel and flexra. Added mds.

File:
1 edited

Legend:

Unmodified
Added
Removed

  • anr/task-2.tex

    r253 r278  
    1212Its objective is to allow the system designer to explore the design space by
    1313quickly prototyping and then to automatically generate the FPGA-SoC systems.
    14 This task consists of
     14This task consists of:
    1515\begin{itemize}
    16 \item The development of all the missing components (SytemC models and/or synthesizable VHDL models
    17 of the IP-cores),
     16\item The development of the synthesizable models required for the connection of
     17the coprocessors on the platform bus (2 bridges).
    1818\item The configuration and the development of drivers of the operating systems (Board Support Package, HAL),
    1919\item The CSG software that generates the SystemC simulators for prototyping and the FPGA-SoC system
    2020including its bitstream and software executable code,
    21 \item The specification of enhanced communication schemes and their sofware and hardware implementations.
    2221\end{itemize}
    23 This task being based on the SoCLib platform, a first release will be delivered at $T0+12$
    24 to allow the demonstrators to start working.
    25 This release will include the standard communication schemes (based on SoCLib MWMR component)
     22A first release will be delivered at $T0+12$ to allow the demonstrators to start working.
     23This release will include the standard communication schemes based on SoCLib MWMR component
    2624and support the neutral architectural template for prototyping and hardware generation.
    2725\end{objectif}
    2826%
    2927\begin{workpackage}
    30 \subtask This \ST corresponds to the COACH System Generator (CSG) software.
     28\subtask{Bridge implementation}
     29    This \ST deals with the development of the synthesizable models required for the connection of
     30    the coprocessors on the platform bus).
    3131    \begin{livrable}
    32     \itemV{0}{12}{x}{\Supmc}{CSG tool} \setMacroInAuxFile{csgCoachArch}
    33         The first software release of the CSG tool that will allow demonstrators to start
    34         working by using the neutral architectural template.
    35     \itemV{12}{18}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgPrototypingOnly}
    36         The second release of CSG supports the \xilinx and \altera architectural
    37         templates and the enhanced communication system, but only for SystemC prototyping.
    38         This release integrates a first integration of HLS tools.
    39     \itemV{18}{24}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgAllArch}
    40         This milestone extends CSG (\csgPrototypingOnly) to
    41         FPGA-SoC generation for the \xilinx and \altera architectural template.
    42     \itemL{24}{36}{x}{\Supmc}{CSG tool}{6:5.5:5.5}
    43         Final release of CSG.
     32    \itemL{9}{18}{h}{\Stima}{HPC hardware \xilinx}{3:9:0}
     33        \setMacroInAuxFile{hpcPlbBridge}
     34        The synthesizable VHDL description of a PLB/VCI bridge.
     35    \itemL{9}{18}{h}{\Supmc}{HPC hardware \altera}{1:2:0}
     36        \setMacroInAuxFile{hpcAvalonBridge}
     37        The synthesizable VHDL description of an AVALON/VCI bridge.
    4438    \end{livrable}
    45 \subtask This \ST deals with the components of the architectural templates.
    46     \\
    47     For the neutral architectural template, it consists of the development of the VHDL
    48     synthesizable description of the missing communication components (MWMR)
    49         in order to support the process network communication model.
    50     Notice that the SystemC models
    51     comes from the SocLib ANR project, the processor with its cache comes from the TSAR
    52     ANR project.
    53     \\
    54     For the \xilinx and \altera architectural templates, we use the \xilinx and \altera IPs (NIOS, Microblaze, memories, busses...).
    55     \begin{livrable}
    56     \itemL{0}{12}{h}{\Supmc}{Neutral architecture}{1:0:0}
    57         \setMacroInAuxFile{csgCoachArchTempl}
    58         The VHDL synthesizable descriptions of the SocLib MWMR, TokenRing components.
    59     \itemL{12}{15}{d}{\Sxilinx}{\xilinx RTL optimisation (2)}{0:2:0}
    60        This deliverable consists in optimizing the VHDL descriptions of the components of
    61        the neutral architectural template (deliverable \novers{\csgCoachArchTempl}) to the
    62        \xilinx RTL synthesis tools.
    63        \upmc will provide the VHDL descriptions, \xilinx will provide back a documentation
    64        listing that proposes VHDL generation enhancements.
    65     \itemV{6}{18}{x}{\Stima}{\xilinx architecture}
    66         \setMacroInAuxFile{csgXilinxSystemC}
    67         The SystemC simulation module of the MWMR component with a PLB bus interface plus
    68         the SystemC modules of the components of the \xilinx architectural template
    69         currently not available in the SocLib component library.
    70     \itemL{18}{24}{h}{\Stima}{\xilinx architecture}{9:9:0}
    71         The synthesizable VHDL description of the MWMR component corresponding to the
    72         SystemC module of the former deliverable (\csgXilinxSystemC).
    73     \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimisation (3)}{0:0:1.5}
    74        This deliverable consists in optimizing the MWMR VHDL description (deliverable
    75        \novers{\csgXilinxSystemC}) of the \xilinx architectural template.
    76        \tima will provide MWMR VHDL description, \xilinx will provide back a documentation
    77        listing that proposes VHDL generation enhancements.
    78     \itemV{6}{18}{x}{\Sirisa}{\altera architecture}
    79         \setMacroInAuxFile{csgAlteraSystemC}
    80         The SystemC simulation module of the MWMR component with an AVALON bus interface plus
    81         the SystemC modules of the components of the \altera architectural template
    82         currently not available in the SocLib component library.
    83     \itemL{18}{24}{h}{\Sirisa}{\altera architecture}{6:6:0}
    84         The synthesizable VHDL description of the MWMR component corresponding to the
    85         SystemC module of the former deliverable (\csgAlteraSystemC);
    86     \itemL{6}{12}{d}{\Subs}{Communication adapter spec.}{1:0:0}
    87        \setMacroInAuxFile{gautCOMMoptimization}
    88        Specification of an optimized communication adapter (space and time) component to handle data interleaving.
    89        This evolution aims to solve out of order communication weakness of the classical MWMR.
    90     \itemV{12}{24}{x}{\Subs}{Communication adapter}{0:6:0}
    91        First release of the tool that generates the VHDL description of the optimized communication adapter
    92        and its corresponding SystemC module.
    93     \itemL{24}{30}{x}{\Subs}{Comm. adapter generator}{0:6:3}
    94        Final release of the tool that generates the VHDL description of the optimized
    95        communication adapter and its corresponding SystemC module (\gautCOMMoptimization).
    96     \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimisation (4)}{0:0:1.5}
    97        This deliverable consists in optimizing the communication adapter VHDL description (deliverable
    98        \novers{\gautCOMMoptimization}).
    99        \ubs will provide communication adapter VHDL description, \xilinx will provide back a documentation
    100        listing that proposes VHDL generation enhancements.
    101     \end{livrable}
    102 \subtask This \ST consists of the configuration of the SocLib MUTEKH and DNA operating
    103     system and the development of drivers for the hardware architectural templates
    104     and enhanced communication schemes defined in \novers{\specCsgManual} deliverable.
     39\subtask{OS setup} This \ST consists of the configuration of the SocLib DNA operating
     40    system and the development of drivers for the hardware architectural templates.
    10541    For the \altera and \xilinx architectural templates, the OSs must also be ported on
    10642    the NIOS2 and MICROBLAZE processors.
    10743    \begin{livrable}
    108     \itemV{6}{8}{x}{\Supmc}{MUTEKH OS}
    109         The drivers required for the first CSG milestone (deliverable \csgCoachArch).
    110     \itemV{8}{18}{x}{\Supmc}{MUTEKH 0S drivers}
    111         The drivers required for the second CSG milestone ({\csgPrototypingOnly}).
    112     \itemL{18}{33}{x}{\Supmc}{MUTEKH OS drivers}{1:1:2}
    113         Final release of the MUTEKH OS drivers.
    114     \itemL{6}{18}{x}{\Supmc}{Porting of MUTEKH OS}{1.0:1:0}
    115         Porting of MUTEKH OS on the NIOS2 and MICROBLAZE processors.
     44%IVG    \itemV{6}{8}{x}{\Supmc}{MUTEKH OS}
     45%IVG        The drivers required for the first CSG milestone (deliverable \csgCoachArch).
     46%IVG    \itemV{8}{18}{x}{\Supmc}{MUTEKH 0S drivers}
     47%IVG        The drivers required for the second CSG milestone ({\csgPrototypingOnly}).
     48%IVG    \itemL{18}{33}{x}{\Supmc}{MUTEKH OS drivers}{1:1:2}
     49%IVG        Final release of the MUTEKH OS drivers.
     50%IVG    \itemL{6}{18}{x}{\Supmc}{Porting of MUTEKH OS}{1.0:1:0}
     51%IVG        Porting of MUTEKH OS on the NIOS2 and MICROBLAZE processors.
    11652    \itemV{6}{8}{x}{\Stima}{DNA OS}
    117         The drivers required for the first CSG milestone (deliverable \csgCoachArch).
     53        The drivers required for the first CSG milestone.
    11854    \itemV{8}{18}{x}{\Stima}{DNA 0S}
    119         The drivers required for the second CSG milestone ({\csgPrototypingOnly}).
     55        The drivers required for the second CSG milestone.
    12056    \itemL{18}{33}{x}{\Stima}{DNA OS drivers}{6:3:2}
    12157        Final release of the DNA OS drivers.
    … …  
    12359        Porting of DNA OS on the NIOS2 and MICROBLAZE processors.
    12460    \end{livrable}
     61%
     62\subtask{Implementation of CSG} This \ST corresponds to the COACH System Generator (CSG) software.
     63    \begin{livrable}
     64    \itemV{0}{12}{x}{\Supmc}{CSG tool}
     65        The first software release of the CSG tool that will allow demonstrators to start
     66        working by using the neutral architectural template only for SystemC.
     67    \itemV{12}{18}{x}{\Supmc}{CSG}
     68        The second release of CSG integrates the VHDL driver for the neutral
     69        architectural template, and an integration of an HLS tools
     70        but only for SystemC prototyping.
     71    \itemV{18}{24}{x}{\Supmc}{CSG}
     72        This release extends CSG to FPGA-SoC generation for the \xilinx and \altera architectural template.
     73    \itemL{24}{36}{x}{\Supmc}{CSG tool}{6:5.5:5.5} \setMacroInAuxFile{csgImplementation}
     74        Final release of CSG enhanced by the demonstrator's feedback.
     75    \end{livrable}
    12576\end{workpackage}
Note: See TracChangeset for help on using the changeset viewer.