source: anr/task-3.tex @ 94

Last change on this file since 94 was 93, checked in by coach, 15 years ago

Fixed anr.bib with most missing references

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1\begin{taskinfo}
2\let\LIP\leader
3\let\IRISA\enable
4\end{taskinfo}
5%
6\begin{objectif}
7The objective of this task is to convert the input specification of
8an hardware accelerator, which must be written in a familiar language
9(C/C++) with as few constraints as possible, into a form suitable for
10the HLS tools. If the target is an ASIP, the frontend has to extract
11patterns from the source code and convert them into the definition
12of an extensible processor. If the target is a process network, the
13front end has to distribute the workload and the data sets as fairly
14as possible, identify communication channels, and output an \xcoach
15description.
16\end{objectif}
17%
18\begin{workpackage}
19  \item This sub-task aims at providing compiler support for custom instructions
20  within the HAS front-end. It will take as input the COACH intermediate
21  representation, and will output an annotated COACH IR containing the custom
22  instructions definitions along with their occurrence in the application.
23
24    \begin{livrable}
25      \itemV{0}{18}{d}{\Sirisa}{Instruction selection for user defined custom instructions}
26        In this first version of the software, the computations patterns corresponding to
27        custom instruction are specified by the user, and then automatically extracted (when
28        beneficial) from the application intermediate representation.
29        %\mustbecompleted{FIXME .....}
30      \itemL{18}{24}{d}{\Sirisa}{Automatic extraction of patterns}{0:0:0}
31        In this second version, the software will also be able to automatically identify
32        interesting pattern candidates in the application code, and use them as custom
33        instructions. 
34    \end{livrable}
35 
36 \item In this sub-task, we provide micro-architectural template models for the two target
37 processor architectures (NIOS-II and MIPS) supported within in the COACH-ASIP design flow.
38 For each processor, we provide a simulation model (System-C) and a synthesizable model (VHDL)
39 of the architecture, along with its architectural extensions
40    \begin{livrable}
41      \itemV{0}{12}{d}{\Sirisa}{SystemC Model for an simple MIPS } 
42      { A SystemC simulation model for an simple extensible MIPS architectural template }
43      \itemV{0}{18}{d}{\Sirisa}{VHDL Model for an simple MIPS}
44      {A synthesizable VHDL model for an simple extensible MIPS architectural template}
45      \itemL{0}{12}{d}{\Sirisa}{SystemC Model for an extensible NIOS processor template, the VHDL model being already available from Altera}{0:0:0}
46          { A SystemC simulation model for an extensible NIOS processor template, the VHDL model being
47          already available from Altera}{0:0:0}
48      \itemV{0}{24}{d}{\Sirisa}{SystemC Model for a complex-MIPS}
49      {A SystemC simulation model for a extensible MIPS with a tight architectural integration of
50      its instruction set extensions}
51      \itemV{0}{24}{d}{\Sirisa}{VHDL Model for a complex-MIPS}
52      {A synthesizable VHDL model for a extensible MIPS with a tight architectural integration of
53      its instruction set extensions}
54      \itemL{0}{36}{d}{\Sirisa}{Evaluation report }{0:0:0}
55      {A evaluation report with quantitative analysis of the performance/area trade-off induced by
56      the different approaches}
57    \end{livrable}
58
59  \item Extraction of parallelism in polyhedral loops and conversion into a process network.
60
61   \begin{livrable}
62    \itemV{0}{6}{d}{\Slip}{Method, Preliminary Definition}
63      Description of the process network construction method for programs with
64      polyhedral loops. User manual.
65    \itemL{30}{36}{d}{\Slip}{Process generation method}{0:0:0}
66      Final assessment of the method and improved version of the user manual.
67    \itemV{6}{12}{x}{\Slip}{Process construction)}
68      Preliminary implementation in the Syntol framework.
69      At this step the software will just implement a single constructor.
70    \itemV{12}{18}{x}{\Slip} {Arrays and FIFO}
71      Implementation of the array contraction and FIFO construction algorithm.
72      Conversion of the input and output to the \xcoach format.
73    \itemV{18}{30}{d+x}{\Slip}{Non-polyhedral extension}
74      Extension of automatic parallelization and array contraction
75      to non-polyhedral loops. Implementation in the Bee framework.
76    \itemL{30}{36}{x}{\Slip} {Process and FIFO construction} {0:0:0}
77      Final release taking into account the feedbacks from the
78      demonstrator \STs.
79   \end{livrable}
80
81\end{workpackage}
82   
83
84
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