Changeset 93 for anr/task-3.tex
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- Feb 4, 2010, 7:14:55 PM (14 years ago)
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anr/task-3.tex
r87 r93 39 39 of the architecture, along with its architectural extensions 40 40 \begin{livrable} 41 \itemV{0}{12}{d}{\Sirisa}{SystemC Model for an simple extensible MIPS architectural template} 42 \itemV{0}{18}{d}{\Sirisa}{VHDL Model for an simple extensible MIPS architectural template} 43 %\mustbecompleted{FIXME .....} 41 \itemV{0}{12}{d}{\Sirisa}{SystemC Model for an simple MIPS } 42 { A SystemC simulation model for an simple extensible MIPS architectural template } 43 \itemV{0}{18}{d}{\Sirisa}{VHDL Model for an simple MIPS} 44 {A synthesizable VHDL model for an simple extensible MIPS architectural template} 44 45 \itemL{0}{12}{d}{\Sirisa}{SystemC Model for an extensible NIOS processor template, the VHDL model being already available from Altera}{0:0:0} 45 46 \itemV{0}{24}{d}{\Sirisa}{SystemC Model for a extensible MIPS with tight 47 architectural integration of its instruction set extensions} 48 \itemV{0}{24}{d}{\Sirisa}{VHDL Model for a extensible MIPS with tight 49 architectural integration of its instruction set extensions} 46 { A SystemC simulation model for an extensible NIOS processor template, the VHDL model being 47 already available from Altera}{0:0:0} 48 \itemV{0}{24}{d}{\Sirisa}{SystemC Model for a complex-MIPS} 49 {A SystemC simulation model for a extensible MIPS with a tight architectural integration of 50 its instruction set extensions} 51 \itemV{0}{24}{d}{\Sirisa}{VHDL Model for a complex-MIPS} 52 {A synthesizable VHDL model for a extensible MIPS with a tight architectural integration of 53 its instruction set extensions} 50 54 \itemL{0}{36}{d}{\Sirisa}{Evaluation report }{0:0:0} 51 55 {A evaluation report with quantitative analysis of the performance/area trade-off induced by 56 the different approaches} 52 57 \end{livrable} 53 58
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