source: anr/task-5.tex @ 120

Last change on this file since 120 was 113, checked in by coach, 15 years ago

IA: updated pour XILINX

File size: 6.1 KB
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1% vim:set spell:
2% vim:spell spelllang=en:
3
4\begin{taskinfo}
5\let\UPMC\leader
6\let\TIMA\enable
7\let\XILINX\enable
8\end{taskinfo}
9%
10\begin{objectif}
11This task pools the features dedicated to HPC system design. It is described on
12figures~\ref{coach-flow} and \ref{archi-hpc}. It consists in
13\begin{itemize}
14\item Providing a software tool that helps the HPC designer to find a good partition of the initial application
15    (figure~\ref{archi-hpc}).
16\item Providing communication schemes between the software part running on the PC and the
17FPGA-SoC. \mustbecompleted{ FIXME :: Quelle difference avec l'item qui suit ???}
18\item Implementing the communication scheme at all levels: partition help, software
19implementation both on the PC and in the operating system of the FPGA-SoC, hardware.
20\item Providing support for dynamic partial reconfiguration of \xilinx FPGA in order
21to optimize FPGA ressource usage.
22\end{itemize}
23
24The low level hardware transmission support will be the PCI/X bus which allows high bit-rate
25transfers. The reasons of this choices are that both ALTERA and Xilinx provide PCI/X IP for
26their FPGA and that GPU HPC softwares use also it.
27\mustbecompleted { FIXME :: ai supprime (mis en commentaire) la phrse qui suivait}
28%This will allow us at least to be inspired by GPU communication schemes and may be to reuse
29%parts of the GPU softwares.
30
31\end{objectif}
32%
33\mustbecompleted { FIXME :: Ne doit onpas fusionner les taches ST6-1, ST6-2, ST6-3 et pourquoi pas ST6-4 ???}
34\begin{workpackage}
35\item This \ST is the definition of the communication schemes as a software API
36    (Application Programing Interface) between the application part running on the PC and
37    the application part running on the FPGA-SoC.
38    \begin{livrable}
39    \itemL{0}{6}{d}{\Supmc}{HPC communication API}{1.0:0:0}
40        \setMacroInAuxFile{hpcCommApi}
41        Specification describing the API.
42    \end{livrable}
43\item This \ST consists in helping to partition applications.
44    It is a library implementing the communication API with features to profile
45    the partitioned application.
46%FIXME (Olivier) pour moi, on veut un outil de profiling pour partitionner l'application.
47% It is a profiling (or simulation) library implementing the communication API
48
49    \begin{livrable}
50    \itemL{6}{12}{x}{\Supmc}{HPC partionning helper}{1:0:0}
51        A library implementing the communication API defined in the {\hpcCommApi} delivrable.
52    \end{livrable}
53\item This \ST deals with the implementation of the communication API on the both sides (PC
54    part and FPGA-SoC).
55    \begin{livrable}
56    \itemL{12}{21}{x}{\Supmc}{HPC API for Linux PC}{0:3:0}
57        The PC part of the HPC communication API that comminicates with the FPGA-SOC, a
58        library and probably a LINUX module.
59    \itemL{12}{21}{x}{\Supmc}{HPC API for MUTEK OS}{0:3:0}
60        \setMacroInAuxFile{hpcMutekDriver}
61        The FPGA-SoC part of the communication API, a driver.
62    \itemL{21}{24}{x}{\Stima}{HPC API for DNA OS}{0:3:0}
63        Port of the {\hpcMutekDriver} driver on the DNA OS.
64    \itemL{24}{33}{x}{\Supmc}{HPC API}{0:0:1}
65        Maintenance work of HPC API for both Linux PC and MUTEK OS.
66    \end{livrable}
67\item This \ST deals with the implementation of hardware and SystemC modules
68    required by the COACH architectural template for using the PCI/X IP of \altera and \xilinx.
69    \begin{livrable}
70    \itemL{9}{18}{h}{\Stima}{HPC hardware \xilinx}{3:9:0}
71        \setMacroInAuxFile{hpcPlbBridge}
72        The synthesizable VHDL description of a PLB/VCI bridge and its corresponding SystemC model.
73    \itemL{9}{18}{h}{\Supmc}{HPC hardware \altera}{1:2:0}
74        \setMacroInAuxFile{hpcAvalonBridge}
75        The synthesizable VHDL description of an AVALON/VCI bridge and its corresponding SystemC model.
76    \itemL{9}{24}{h}{\Supmc}{PCI/X traffic generator}{1:1:0}
77        The SystemC description of a component that generates PCI/X traffic. It is
78        required to prototype FPGA-SoC dedicated to HPC.
79    \end{livrable}
80
81\item This \ST consists in integrating dynamic partial reconfiguration of \xilinx FPGA in the CSG design flow.
82It also includes appropriate SoC-FPGA OS drivers and a modification of the profiling library.
83    \begin{livrable}
84    \itemL{24}{36}{x}{\Supmc}{CSG support for \ganttlf reconfiguration}{0:0:2}
85        Modification of CSG software to support statically reconfigurable task.
86    \itemL{18}{36}{x}{\Stima}{CSG module for \ganttlf dynamic reconfiguration}{0:6:12}
87                This livrable is a CSG module allowing to partition the task graph on
88                the dynamic partial reconfiguration regions. The resulting task-region assignement
89                is directly used for generation of bitstreams. The module also produces reconfiguration
90                management software to be run on the SoC-FPGA.
91    \itemL{18}{30}{x}{\Stima}{dynamic reconfiguration \ganttlf DNA drivers}{0:3:3}
92        \setMacroInAuxFile{hpcDynconfDriver}
93            The drivers required by the DNA OS in order to manage dynamic partial
94        reconfiguration inside the SoC-FPGA.
95    \itemL{30}{36}{x}{\Supmc}{dynamic reconfiguration \ganttlf MUTEK drivers}{0:0:1}
96        Port of the {\hpcDynconfDriver} drivers on the MUTEK OS.
97    \itemL{24}{36}{x}{\Stima}{Profiler for \ganttlf dynamic reconfiguration}{0:0:6}
98        Extension of the HPC partionning helper in order to integrate dynamic partial
99        reconfiguration dedicated features (reconfiguration time of regions, variable
100        number of coprocessors).
101    \itemL{24}{36}{d}{\Sxilinx}{optimisation for \ganttlf \xilinx dynamic reconfiguration}{0:0:1}
102        \xilinx will work with \tima in order to better take into account during
103        partitioning decisions specific constraints due to partial reconfiguration process.
104        The delivrable is a document describing the \xilinx specific constraints.
105    \end{livrable}
106%\item This \ST is the delivery of 2 PCI/X \mustbecompleted{FIXME: Stratix4} FPGA board
107%   with its PCI/X IP. These boards are dedicated to the COACH HPC development.
108%   They are based on \mustbecompleted{FIXME:stratix4} FPGA device of 400,000 LUT.
109%   \begin{livrable}
110%   \itemL{0}{6}{m}{\Saltera}{HPC development boards}{0:0:0} Two PCI/X FPGA boards.
111%   \end{livrable}
112\end{workpackage}
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